Complete 3D co-design capabilities
Allegro Package Designer provides true integration with IC development in a physical co-design environment to help engineers make strategic tradeoffs earlier and with greater confidence.
Cadence® Allegro® Package Designer integrates with First Encounter® Silicon Virtual Prototyping to deliver chip-level I/O feasibility planning capabilities in an industry-proven co-design methodology. Data integration with First Encounter technology provides mask accuracy in the RDL routing and improves I/O pad ring optimization, substrate interconnect design, extraction, modeling, and signal integrity analysis. The final design output provides automatic system-level handoff's for PCB design.
Features/Benefits
- Supports a full front-to-back IC/package physical co-design flow
- Determines the best package and substrate options early in the IC design cycle
- Provides comprehensive design rule- and electrical constraint–driven layout
- Incorporates design for manufacturing (DFM) methodologies
- Optimizes I/Os at the die bump level with a package-driven flow
- Improves design flow with intrinsic support for all industry standards
- Models entire design with Cadence 3D Design Viewer
Allegro Package Designer is available in the following configurations:
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Provides an entry-level configuration of the industry's leading design system for complete IC/package design. |
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Extends the L family to enable true IC and IC package co-design allowing designers of today's complex, leading-edge devices to meet cost, performance, and time-to-market goals. Includes chip-level I/O planning capabilities and an embedded 3D field solver. |