Complete environment for concurrent co-design between IC and Package
Cadence Allegro® Package Designer products streamline IC package design and IC package co-design. They comprise a complete constraint-driven physical design solution that supports virtually all packaging methods as well as 3D viewing and 3D wirebond design rule checks
The Allegro Package Designer combines chip-level I/O feasibility planning capabilities with industry-leading IC package tools to deliver a proven co-design methodology integrated with Cadence® First Encounter. This family of products also includes an embedded technology leading 3D field solver that allows engineers to quickly create full package-level simulation models that can help PCB designers trade off electrical performance versus size and cost. As performance targets for today's devices increase, demand for more accurate models grows. Cadence is committed to meeting those demands today and in the future.
Allegro Package Designer is available in the following configurations:
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Provides an entry-level configuration of the industry's leading design system for complete IC/package design. |
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Extends the L family to enable true IC and IC package co-design allowing designers of today's complex, leading-edge devices to meet cost, performance, and time-to-market goals. Includes chip-level I/O planning capabilities and an embedded 3D field solver. |