Designers of high-end consumer electronics face the challenge of miniaturization and its resulting complexity. The number of nets on a printed circuit board (PCB) that have high-speed constraints is growing. As the industry migrates to multi-gigabit serial interfaces like PCI Express, the number of constraints on nets is also increasing. And as consumers demand ever-smaller gadgets packed with amazing features, complex die stacking is paramount to an IC packaging strategy. Today’s PCB and package designers need a complete high-density interconnect (HDI) solution that includes high-speed rules, manages faster data throughput, and offers advanced routing capabilities to shrink footprints and meet aggressive market windows.
With an array of new features and functionalities, the Cadence® Allegro® and OrCAD® PCB Design Release 16.3 and Allegro IC Packaging/SiP Design Release 16.3 give designers more flexibility to meet the challenges of high-speed design miniaturization with the utmost in productivity and predictability. Enhancements for flex-rigid routing, 3D design viewing, flip-board editing, and easier set-up are just a few of the benefits. The 16.3 release will be available at downloads.cadence.com and through Cadence channel partners starting early December 2009.
“We participated in the multi-phase beta program for the version 16.3 and were very impressed,” says Vincent Di Lello, senior PCB designer at Kaleidescape Canada, Inc. “The improvements in this new version address our miniaturization design challenges very well, and we look forward to adopting this new release into our design flow at the earliest opportunity.”
Check out the video interviews announcing everything new in the 16.3 release. View 16.3 feature videos »
Accelerating product miniaturization
The 16.3 release addresses design challenges associated with miniaturization through improvements for rigid-flex routing, extended HDI rules, 3D viewing of PCBs, and asymmetrical clearances for RF circuits. Extended micro-via stacking rules allow users to create the most difficult HDI designs, and multi-line curved bus routing that hugs the flex outline accelerates the creation of rigid-flex designs. Additionally, an integrated 3D PCB viewer gives designers visibility into components and HDI micro-via breakouts, eliminating unnecessary iterations with mechanical design teams. Now with asymmetrical clearances for one or more RF elements, the Allegro PCB RF Option helps engineers create accurate RF circuits more quickly.
“This latest Allegro/OrCAD release provides many improvements to address miniaturization design challenges on a rigid or rigid-flex design,” explains Scott Miller, COO of Freedom CAD. “As a design services company, we are always interested in improving our designer productivity and design process predictability. We will be moving to 16.3 and also recommending our customers to migrate soon.”
Boosting productivity and ease of use
Beyond general usability improvements, OrCAD Capture and Capture CIS now offer 3D component footprint symbol viewing and autowiring (automatic wiring of a connection on a schematic page). Conventionally, a connection is made between component pins by clicking from point to point to point—a tedious and time-consuming task. With the new autowire functionality, wiring between component pins is as simple as selecting a starting pin and a destination pin, and then letting the software add the connection—fast and automatic.
OrCAD PCB Editor has also been enhanced with usability improvements including flip-board viewing and editing and full 3D PCB viewing to eliminate unnecessary iterations. Flip-board capability allows designers to physically flip the board inside the design database. The board is still in 2.5D, but it is literally upside-down. The benefit is that everything on the bottom of the board is right-reading. And since all the editing capabilities are still intact, designers can continue to work on the board, even in its upside-down state. The Cadence PSpice® product underwent a complete makeover of its waveform environment along with enhanced cursor support and new simulation models.
On the Allegro side, the front-end design authoring flow (including analog/mixed-signal circuit simulation) received a usability and productivity overhaul, enabling a single schematic for simulation and layout. Allegro Signal and Power Integrity software boosts productivity through a new user interface and new stack-up-aware capabilities in the pre-route analysis environment. Updates to Allegro Design Workbench optimize library and design data management. Integrated ECAD-MCAD part creation, generation, and distribution allows mechanical part classification and electronic part association for unified BOM generation. Engineers have earlier access to pre-released/temporary parts, and they can be notified of obsolete part status during the logic authoring process and easily implement changes.
Optimizing IC packages and SiPs
For the IC packaging and SiP environment, 16.3 features a new product—SiP Layout XL—which adds a co-design methodology to the package design environment and introduces “super-smooth” routing technology. Allegro Package Designer now features an SiP finishing mode to ease data exchange among design chain partners.
“We are looking forward to adopting the 16.3 release so we can improve our productivity and provide better IC package co-design service to our customers,” says CT Chiu, R&D product design manager of Advanced Semiconductor Engineering (ASE). “We anticipate the new Cadence SiP and IC packaging technology to play an important role in streamlining the semiconductor design chain.”
Join us at the Allegro/OrCAD cyber conference for what’s new in 16.3
The launch of 16.3 release culminates on December 2, 2009 with a full-day virtual event, where participants can remotely attend live keynote presentations within a virtual conference hall and visit booths of interest within a virtual exhibition hall—all from the comfort of their own computers. The event will include papers, presentations, and demonstrations from Cadence technologists, strategic partners, and industry experts, with whom you can chat directly throughout the day. Register now to save your spot at this exclusive event.
