Modules
Graphic Station
The Graphic Station provides powerful tools in an easy-to-use, easy-to-learn high-power graphic user interface. View and manipulate intelligent ODB++ data to maximize efficiency and productivity with accurate capture and display of all the relevant CAD/CAM/EDA entities. Navigate through a true-to-life representation of the board on your monitor and conduct a variety of operations (measurement, analysis and optimization of data, selection and filtering, and much, much more). Includes full panelization and drill/rout programming capabilities.
CAD Database Input Interface
Eliminates Gerber, Component Placement Lists, and CNC Files as a Data Transfer Format.
CAD Database Input Interfaces provide direct input and read capabilities for Mentor Boardstation, PowerPCB, Zuken "evaluated" and “non-evaluated” Cadif, PWS and BD, and Cadence Allegro databases into ODB++. Reverse engineering of data between CAD and CAM based on old “legacy” formats is eliminated. Enterprise captures all of the CAD data and design intelligence necessary for successful PCB fabrication, assembly and test and puts it in a single ODB++ job directory. Critical information such as nets associated with features, component and pin information for every pad, geometry names, hole plating information, and more, is now available to extend ODB++ capabilities for vertical integration of design, fabrication and assembly.
BOM Manager
Integration of procurement-BOM with CAD data.
Bills Of Material (BOM) and Approved Vendor Lists (AVL) can come in a wide variety of forms, layouts and syntaxes. The BOM Manager provides a comprehensive set of tools to read incoming logistical data files -regardless of format - based on intelligent logic-driven templates. Following parsing, BOM/AVL data is set against the Valor Parts Library for validation. Once saved in a validated form, the BOM file is ready for input to the ODB++ jobs database of the Graphic Station, for accurate DFM analysis using VPL package models.
Parts Library Manager
Open customization access to the VPL.
The VPL supports extensive customization, either to create and manage extended process-attributes of the packages within your local library, or for creation of package entities for your customized or specialist components. The Parts Library Manager provides full functionality for definition of component parts and packages, according to the same principles as used by Valor in its centralized VPL-support operation.
CAM Data I/O Package
Intelligent translators support all commonly used CAM formats.
When reading of a series of CAM or machine-level formats is required, either in parallel to ODB++ or for the purpose of "reverse-engineering" a design, Enterprise 3000 provides automatic, intelligent input of all commonly-used formats: HP-GL, Gerber RS274D/X, Excellon, Sieb&Meyer, DXF, IPC-D-356, and many more. Likewise when it comes to output - if machine-level formats are needed for sending into production, either instead of ODB++ or in parallel, Enterprise 3000 supports the needs of the industry with outputs for HP-GL, DXF, Postscript, Excellon, Gerber RS274D/X, IPC-D-356. Receiving or outputting data has never been easier.
3D VRML Simulator
View the product in 3D throughout the design stage, before committing to prototypes!
Using sophisticated 3D visualization tools based on Virtual Reality Modeling Language (VRML), Enterprise 3000 provides the technology to view the assembled board just after the component placement stage of design. Checking the designs in this way provides a quick and visually rich means of assessing component layout relative to assembly requirements. Fix placement issues before investing time in laying out the interconnections. Valor provides an open industry standards based solution. VRML files can be passed to the manufacturers for viewing to enhance DFM and pre-tooling engineering work.
Graphic Synchronization
Graphical hot-links between Enterprise 3000 and your CAD-layout system integrate DFM as a concurrent tool on the Designer’s desktop.
Once you’ve read the CAD database into ODB++, Enterprise 3000 provides intelligent graphical links directly to the CAD system. All it takes is the touch of a key and any design feature can be reviewed with identical zoom and positioning in the CAD system and Enterprise. Graphic Synchronization enables rapid review of DFM results from within your native PCB layout environment, maintaining data consistency and integrating Enterprise 3000 as a concurrent "plug-in" tool on the designer’s workstation.
CAD DataBase Output, IDF 2.0 and 3.0 M-CAD format
Deliver a full physical model of the PCB Assembly to M-CAD systems.
Intermediate Data Format (IDF) is the recognized de facto standard for communication between mechanical CAD systems and electronics CAD. This output option facilitates back-annotation of the full Printed Circuit Assembly physical model from ODB++ into well-known M-CAD applications such as Pro-Engineer, AutoCAD, AutoDesk etc.
Sharelist HTML, XML and ASCII output interface
Output of DFM collaboration results for exchange across distributed workgroups.
Share list operates within the Graphic Station to capture selected DFM analysis results and package them in an open document format for effective engineering collaboration. Combining graphical text/numerical data records, Share list also includes user comments and suggestions. Output formats include HTML, XML, and formatted ASCII.
Graphic Station Automation License
Double your DFM process productivity.
Enables scripts to drive the system by line-mode commands, and also use of the powerful “info” command, which queries the ODB++ database for records to drive decision-loops in automation routines.
Assembly/Test Analysis
Advanced Manufacturability Review for the Assembly Process
Using ODB++ intelligence, augmented by VPL true package models, the system's advanced Assembly/Test Analysis programs allow any user to catch manufacturing defects before the product arrives on the manufacturing floor. Assembly/Test Analysis programs deal with problems unique to assembly such as component spacing, fiducials, test points, outlines, etc. This powerful package delivers extensive reports and full automation for over 100 categories in 5 major actions: Fiducial Analysis, Component Analysis, Padstack Analysis, Testpoint Analysis and Solder Paste Analysis.
Bare-Board Analysis
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HDI (High Density Interconnect) Fabrication Analysis
HDI and BGA/COB analysis package.
An upper-level analysis package, suitable for BGA-substrate and chip-on-board (COB) applications, appropriate to conventionally-laminated multi-layers and also sequential-build-up technology. HDI Fabrication Analysis extends the range of physical verification analyses to check minimum etch spacings between all combinations of feature type (selected by attribute), including spacings between solder-mask, all categories of conductive features, and components. Conductor angles are verified against pre-set criteria, and analysis takes into account whether layers are core-type or build-up.
HDI (High Density Interconnect) Microvia Analysis
Buried/Surface/Blind vias analysis package.
HDI Microvia Analysis extends the range of drill analyses to check for spacing, annular ring characteristics of al types of microvia, sorted by type and position in the substrate build-up. Microvia analysis takes into account whether layers are core-type or build-up, and the proximity of holes to each other, even when placed in different layers.
Net List Analyzer
Compares netlist data to provide electrical integrity assurance.
Netlist Analyzer uses real-time rasterization techniques to extract a true interconnectivity map of any PCB in a matter of seconds. Compare this to any reference netlist you want (such as the logical netlist from the CAD system included in the original data), and the system reports and highlights the differences so that you can easily pinpoint graphical elements responsible for any flaws in netlist integrity, like opens or shorts. A powerful tool which gives the PCB designer the ability to verify final data integrity before manufacturing sign-off.
Signal Quality Analysis
Verify signal quality/integrity aspects of the ODB++ physical model.
Signal Quality Analysis provides qualitative checks of physical layout characteristics to find aspects of the board design which may be harmful to overall signal integrity. Permits the critical ability to apply spacing criteria which vary relative to signal characteristics.
Solder Stencil Design
Optimize the soldering process, based on full ODB++ intelligence.
Subtle differences in solder paste size and shape have significant impact on soldering yield. Taking into account component type, footprint and pad shapes, Solder Paste Optimization changes the solder paste objects to best match the process constraints representing stencil thickness, paste type, print speed etc. Percentage coverage of solder paste, as well as aspect ratio limits, are controlled across the board.
Sliver Fill DFM Program
Eliminates slivers, incomplete shaves and acid traps.
Sliver-Fill DFM provides an automated solution for dealing with small or extremely narrow pieces of resist, which can easily peel from the surface of the layer and cause shorts or other connectivity problems. Four sub-actions offer protection against a variety of sliver types, from acute angles to legend conflicts.
Line Width Optimizer DFM Program
Automated line width modification for optimized yield.
Line Width Optimizer not only improves yield and increases productivity, but actually expands fabrication capabilities to include fine line and high density boards. Use Line Width Optimization to rapidly and automatically detect and edit critical design rule violations without creating secondary conflicts. Neckdowns and trimdowns are created automatically where necessary to preserve board integrity. Another Valor automated solution for slashing pre-production time and sharpening your competitive edge.
Etch Compensation DFM Program
One-step etch compensation on relevant elements on relevant layers
Etch Compensation DFM offers an out-of-the-box automation solution for compensating feature width for over-etching while preserving critical manufacturing parameters and design rules. Advanced mathematical and algorithmic libraries contained in the ODB++ facilitate all changes while preserving net list and spacing rules. Shavedowns are automatically applied to problematic areas. Bottom line benefits are reduced cycle time, increased yield, and dollar savings.
Copper Balancing DFM Program
Automatically generates pattern fill for uniform plating process.
Copper Balancing takes full control of the process of placing extra copper for more economical, more effective chemical processing. As circuit thickness increases and through hole component density increases, the aspect ratio of panel thickness to hole diameter also increases. Uneven copper distribution compromises current density during plating, causing a gamut of problems. Put Copper Balancing to work to reduce editing time and increase plating and process yield.
Pin Hole Elimination DFM Program
Increase yields by eliminating small openings and conductor-islands.
Features and ground planes often contain small pinholes (data does not overlap) or islands of conductive material (when data is in opposite polarity). Trying to repair these pinholes manually consumes countless hours of unreliable interactive graphical editing. Aided by shape-based, rules-driven algorithms, the Pin-Hole Elimination DFM program automatically searches through a design for any pinhole or island according to dimensional search criteria. Detected errors are repaired automatically.
Solder Mask Optimization Program
Minimize solder-bridges, maximize process-yield.
Solder masks based on apertures maintained in padstack libraries can create overlaps (solder-bridge risk), spacing violations (cannot be imaged on the board), or annular clearance problems (reducing the ability to manufacture large, cost-effective panels). Solder Mask Optimization eliminates hours of tedious interactive work to achieve a producible board, by running rules-driven modification algorithms to optimize a design in a matter of seconds.
Legend Detection DFM Program
Powerful DFM Program automatically recognizes non-critical features.
Legend Detection DFM consolidates the recognition and identification of non-PCB features (particularly text and legend characters) into a brisk, effortless, one-time operation. With out-of-the-box convenience, Legend Detection analyzes affected layers automatically, detects text/ nomenclature and assigns an attribute. This attribute stays with the feature throughout the life of the job, making subsequent DFM analysis, optimization and tooling functions more accurate and predictable.
Silk Screen Optimization DFM Program
Rapid, automatic silk screen clipping maintains board integrity and fabrication tolerances.
Silk screen layers are often output from CAD/EDA systems without a check of critical features such as pads or via-holes overlapped by data. These problems must be solved to prevent poor solderability, or dry joints. Silk Screen Optimization replaces traditional methods such as solder mask negative merging, by clipping the data according to spacing rules which respect screen-mesh resolution and maintain positive data polarity.
Redundant Line Removal DFM Program
Removes vectors fully contained in other shapes.
Redundant Vector Removal DFM removes non-functional vectors to clean up over-heavy vector data. This ready-to-use solution works quickly and efficiently, from preset or user-defined constraints, globally or point-by-point. Superfluous lines resulting from pattern filling of EDA data with algorithmic limitations and sub-optimal Gerber output translation clog memory to slow processing and lengthen cycle time. Redundant Vector Removal provides the best available solution.
Signal Layer Optimization DFM Program
Maximize annular rings, conductor clearances, for maximum yield.
All it takes is a few localized features of a board layout to cause the difference between a board that is manufacturability, and a board that is virtually impossible to actually create. Taking into account constraints to respect spacing, allow/disallow local-rerouting, allow negative shaves, etc., Signal Layer Optimization respects spacing, allow/disallow local rerouting, allow negative shave, and other pertinent constraints to perform localized relaxation algorithms, globally or locally. Spacing/ annular ring hot-spots are eliminated, and the manufacturability of a touch design is dramatically increased.
Power and Ground Optimization DFM Program
This DFM function optimizes the features on voltage layers for manufacturability while maintaining all rules of minimum electrical connectivity, spacings and bridges across clearances etc. Layer registration and drilling tolerances are expanded, without affecting functional design requirements.
Neck Down Repair DFM Program
Eliminate conductivity hot spots in the physical design model.
When PCB layer data is moved from the logical model of the CAD system into the physical model of ODB++ or Gerber, neckdowns often appear where vectors are not fully driven home into pads or planes. To eliminate the possibility of localized electrical failure, or longer-term field-failure, Neck-Down Repair searches out all local conductor neckdown locations using shape-based algorithms, implementing localized graphical repair to maintain full width connectivity.
Line Unification DFM Program
Unifies parallel lines and overlapping lines.
Automated Line Unification enhances productivity by reducing job complexity caused by superfluous lines occurring as a result of sub-optimal Gerber output (limited aperture wheel). Once parameters are defined, powerful automation kicks in to globally clean data and correct CAD/EDA post processing errors. Line Unification DFM reduces the complexity of board data in such cases by an average of 1:10.
DFM Programming Environment
Advanced automation development tool for easy development of in-house solutions.
The DFM Programming Environment is a C-based programming tool which grants system users full access to the ODB++ database, including advanced internal math and algorithm libraries, to create fully compiled in-house automation solutions. The DFM Programming Environment, the same tool used by Valor R&D to create most of the automated DFM solutions available for the system, interfaces seamlessly with the user interface. New actions are identical to existing actions in terms of how they function within the Enterprise 3000 GUI. Valor R&D continually updates the DFM Programming Environment, enriching programming capabilities and adding categories and DFM calls. View the related fact sheet for a partial list of the available system calls.
WorkForms
Interactive teamware emulating paper forms extended across the Internet.
Easy to create, easy to apply Work Forms feature advanced graphics and interactive hot buttons to create electronic forms which emulate familiar paper forms, fully portable over the Internet or Intranet. Updates are instantly reflected at every workstation or terminal; callback functions provide seamless integration with user-defined scripts, DFM programs and third party packages. A simple link on an HTML page on the user's web server activates the client side of the Java applet, incorporating a secure login mechanism and allowing easy flow of information to your customer for approval. A single master copy is stored in the ODB++, ready to be copied, updated, or applied to any job within the system.
ERF Manager
Rules Management for maximum DFM efficiency
A vital system-support tool for Enterprise 3000 users. ERF Manager supports efficient management of DFM analysis and optimization rules, delivering user-friendly rules-entry and review, including logical checking routines to monitor the rules-editing process.