"Designed with OrCAD of course!"

Ryan Dunwoody - Pi-Top

“With Allegro TimingVision, the routing process has sped up dramatically, from four weeks, down to four days,”

Bill Munroe - Cavium

Designed with Cadence.
Download design files here...

“We’re very optimistic about our future with the scalable OrCAD PSpice and Allegro PCB Designer tools"

The Cadence solution reduces our PCB development time by 80 percent

- Gisbert Thomke, Group Leader, IBM R&D Lab

Designed with Cadence OrCAD and Allegro since 2003

Now recruiting for Cadence engineers

OrCAD Classroom Training Courses

ArrowArrow
ArrowArrow
Shadow
Slider

Matrix Key: A tick confirms that the feature is included in the suite. An option name (CIS Option for example) means you need to purchase the option to get the feature included in the suite

Cadence PCB Suite Configuration Matrix
LICENSING AND SUPPORT OrCAD Standard OrCAD Professional Allegro Designer
Floating Networked License
12 Months Maintenance Support Included In Purchase Price
SCHEMATIC ENTRY + DATA MANAGEMENT Standard Professional Designer
Graphical, flat and hierarchical page editor and Picture block hierarchy
OrCAD Marketplace to download OrCAD apps
OrCAD PSpice AD Lite (up to 75 nodes)
Net Groups - Complex bus definition
AutoWire
44,000 Schematic symbols
Coloured Components / nets
Tcl TK scripting support
Online design rule check including custom DRC capability and Waive DRC
Forward and back-annotation of properties / pin-and-gate swaps
Schematic Part and Library editor
Cross-probing and cross-placing
FPGA design-in / pin import & export
Multiple PCB netlist interfaces
SI Topology creation
Digi-Key (PartLink App) Component Parametric data directly from web
Property editor for pins, components, nets
OrCAD SigXplorer SI Analysis
Intelligent PDF creation Updated in 17.2 Updated in 17.2 Updated in 17.2
Advanced Annotation New in 17.2 New in 17.2 New in 17.2
Design Compare (detail and Graphical) New in 17.2 New in 17.2 New in 17.2
Default Demo designs New in 17.2 New in 17.2 New in 17.2
Extended Preferences New in 17.2 New in 17.2 New in 17.2
Export ISCF (Intel Schematic Connectivity Format) New in 17.2 New in 17.2 New in 17.2
Export / Import XML New in 17.2 New in 17.2 New in 17.2
Altium Importer Schematic (PCB also available)
Eagle Importer Schematic (PCB also available)
OrCAD PSpice AD Lite (up to 75 nodes)
Component Information System CIS option CIS option
Windows ODBC compatible format CIS option CIS option
Interface to relational database and management systems CIS option CIS option
Database query for part selection and parametric properties CIS option CIS option
Schematic and BOM Variants Manager (Parts not Fitted and more). CIS option CIS option
CIS Database Management Interface (access control and more) CIS Option + CIP E Option CIS Option + CIP E Option CIP E Option
Part search DIGIKEY, FARNELL, FUTURE, MOUSER, ARROW CIS Option + CIP E Option CIS Option + CIP E Option CIP E Option
PCB EDITOR Standard Professional Designer
Physical, Spacing, Same net, Netclass and Class to Class rules Updated in 17.2 Updated in 17.2 Updated in 17.2
DFM Pad Entry / Exit Rules Updated in 17.2 Updated in 17.2 Updated in 17.2
Dynamic pad suppression / Unused Pad removal Updated in 17.2 Updated in 17.2 Updated in 17.2
Cross Section Editor Updated in 17.2 Updated in 17.2 Updated in 17.2
Padstack Editor IPC2581 Compliant Updated in 17.2 Updated in 17.2 Updated in 17.2
Customisable Visibility Pane Updated in 17.2 Updated in 17.2 Updated in 17.2
Dynamic Shape Pin Connection By Layer (Global/Shape/Pin/Layer) Updated in 17.2 Updated in 17.2 Updated in 17.2
Dynamic Cross Hatch Shapes Updated in 17.2 Updated in 17.2 Updated in 17.2
Interactive Routing using Working Layer (layer selection popup)
Multiple placement options, manual, quickplace, auto and room
Placement directly from schematic, individually or window select
Dynamic Shapes (dynamic copper pours) Plow and Heal
Push, Shove and Hug interactive editing
Embedded net names
Curve Routing
Auto Finish (Route Completion Tool)
Through Board Transparency (OpenGL)
Multi‐line routing (Group Routing)
Fan‐out generators
Flip Board
Excellon NC Drill File export
Gerber 274X, 274D artwork Output
IPC2581 Import / Export
Mentor® ODB++ and universal viewer
DFM Checks including soldermask, solderpaste and more
Dynamic rat suppression
Move with autoroute adjust (Slide)
Route cleanup, optimization (Glossing) Updated in 17.2 Updated in 17.2
Impedance Calculator
Interactive / Automatic Silkscreen generation
Blind Buried Single Click multiple via instantiation
Manual Design For Test (DFT) / Test Prep
Component Height DRC
Aligment x and y for components and modules
Associative Dimensioning
Split View
Snake Routing for Hex pattern ICs
Import Altium PCB (schematic also available)
Import EAGLE PCB (schematic also available)
Import PADS & PCAD
Import IFF RF Shapes
Import Export DXF
MCAD/ECAD Incremental design data exchange (IDX)
Import Export IDF
STEP 3D viewer for selected item or complete PCB.
STEP 3D In/Out Updated in 17.2 Updated in 17.2 Updated in 17.2
Application Mode (General, Etch, Placement)
Application Mode (shape)
Scribble Sketch Routing
Full Skill Support
Group route Bus Route and via patterns New in 17.2
Line Fattening New in 17.2 New in 17.2
Differential Pair Static Phase Control rules New in 17.2
Differential Pairs Physical rules and routing New in 17.2
Propagation delay rules (Relative) for nets or groups
Propagation delay rules (Min/Max) for nets or groups
Dynamic Heads‐up Display for critical rules
Hug Contour routing (Flex)
Shape based curve fillet support, tapered traces
Placement replication, template based design reuse
Constraint Regions, region based rules (Rigid‐Flex; BGA regions)
Total Etch Length - Max/Min Length
Delay Tuning
Automatic Design For Test (DFT) / Test Prep
Impedance Single Ended Worksheet
Net Scheduling, T‐Point rules (pin to T‐point), T-Point definition
Via array / Shielding - Shape and Trace based
Extended (X)net rules
Pin Pair rules
Segment over void detection New in 17.2
Spread lines between voids New in 17.2
Multi Cross Section support for Rigid Flexi New in 17.2 New in 17.2
Rigid Flexi Zone Management New in 17.2 New in 17.2
Dynamic Zone Placement New in 17.2 New in 17.2
Inter Layer Checks for Rigid Flexi New in 17.2 New in 17.2
Layer set rules New in 17.2
Dynamic Phase Control rules
CAD Translators - Import Mentor® Boardstation
Max Via Count rules
Dynamic DFA rules based interactive placement
Offset Routing
Design planning ‐ Create hierarchical Bundles
Design planning ‐ Create, Edit Flows
Design planning ‐ Assign Flows to Layers
Dynamic Shape based curve fillet support, tapered traces
Backdrilling Updated in 17.2
Design Planning ‐ Plan Spatial Feasibility analysis & feedback Design Planning Option
Design Planning ‐ Generate Topological Plan Design Planning Option
Design Planning ‐ Convert Topological plan to traces (CLINES) Design Planning Option
Auto Connect (Breakout, Connect, Compress, Spread, Nudge, Push) Design Planning Option
Auto Interactive Break-out (AiBT) Design Planning Option
Automatic Delay Tune (AiDT) PCB High-Speed Option
Automatic Phase Tune (AiPT) PCB High-Speed Option
Package Pin Delay (for die‐2‐die delay) rules PCB High-Speed Option
Z‐Axis delay feedback PCB High-Speed Option
Remove Tuning PCB High-Speed Option
Timing Vision (Coloured tracks based on constraint adherence) PCB High-Speed Option
High Speed Via Structures PCB High-Speed Option
Via Voiding Differential Pairs PCB High-Speed Option
Tabbed Routing PCB High-Speed Option
Single net Return Paths Vias PCB High-Speed Option
Electrical Constraint rule set (ECSets) / Topology Apply PCB High-Speed Option
Electrical rules (Reflection, Timing, Crosstalk) PCB High-Speed Option
Advanced Constraints (formulas, relational) PCB High-Speed Option
Fabric Weave Effect Zig Zag Auto Interactive PCB High-Speed Option
Differential Pair Return Path Vias PCB High-Speed Option
Constraint Manager: HDI rule set Miniaturization Option
Micro-via and associated spacing, stacking and via-in-pad rules Miniaturization Option
Constraint driven HDI design flow Miniaturization Option
HDI micro-via stack editing Miniaturization Option
Manufacturing rule support for embedding components Miniaturization Option
Embed components on inner layers Miniaturization Option
Support for Cavities on inner layers Miniaturization Option
Support for Vertically placed components on inner layers Miniaturization Option
Soldermask for embedded components New in 17.2 Mini Option
Support for copy and swap embedded components New in 17.2 Mini Option
Dual Side Contact Embedded Components Miniaturization Option
Concurrent Team Design ‐ Layer by Layer PCB Team Design Option
Concurrent Team Design ‐ Functional block partitioning PCB Team Design Option
Concurrent Team Design ‐ Team design dashboard PCB Team Design Option
Concurrent Team Design ‐ Soft boundaries PCB Team Design Option
Concurrent Team Design - Constraint Editing and Netclasses per Partition PCB Team Design Option
Harmony Team Design New Option in 17.2 2016 Harmony Team Design Option
Swap pins on a FPGA (based on FPGA rules) in PCB Editor FPGA System Planner
Reoptimize pins on a FPGA (using FPGA rules) FPGA System Planner
Parameterized RF etch elements PCB Analog / RF Option
Asymmetrical Clearances PCB Analog / RF Option
RF Etch elements editing PCB Analog / RF Option
Bi‐Directional interface with Agilent ADS PCB Analog / RF Option
ADS schematics Import Agilent into DE‐HDL PCB Analog / RF Option
Layout‐driven RF design creation PCB Analog / RF Option
Flexible Shape Editor PCB Analog / RF Option
PSpice SIMULATION Standard Professional Designer
OrCAD PSpice AD Lite (up to 75 nodes)
Bias Point, DC sweep, AC sweep & transient analysis (with Temperature) PSpice AD PSpice AD PSpice AD
Parametric Analysis PSpice AD PSpice AD PSpice AD
Learning PSpice Free Templates PSpice AD PSpice AD PSpice AD
Analog behavioural modelling PSpice AD PSpice AD PSpice AD
Stimulus editor PSpice AD PSpice AD PSpice AD
Model Editor for device characterization PSpice AD PSpice AD PSpice AD
Interactive waveform viewer & analyzer PSpice AD PSpice AD PSpice AD
IBIS / DML model support PSpice AD PSpice AD PSpice AD
Monte Carlo: Statistical circuit behaviour and yield (Worst Case) PSpice AD PSpice AD PSpice AD
Bias point voltages, currents and power display on schematic PSpice AD PSpice AD PSpice AD
Sensitivity: Identifies critical circuit components Advanced Analysis Advanced Analysis Advanced Analysis
Optimizer: Optimizes key circuit components Advanced Analysis Advanced Analysis Advanced Analysis
Monte Carlo: Statistical circuit behaviour and yield multiple measurements Advanced Analysis Advanced Analysis Advanced Analysis
Smoke: Detects component stress Advanced Analysis Advanced Analysis Advanced Analysis
Parametric Plotter: Examine solution through nested sweeps Advanced Analysis Advanced Analysis Advanced Analysis
Optimize Circuits through Curve or Parameter Fit Advanced Analysis Advanced Analysis Advanced Analysis
Example Design Simple Circuit 1
Example Design Simple Circuit 2
Example Design Simple Circuit 3
Example Design Simple Circuit 4
Example Design Simple Circuit 5
Example Design Simple Circuit 6
Example Design Simple Circuit 7
SIGNAL INTEGRITY Standard Professional Allegro Designer
Pre- & Post-route signal integrity analysis
Graphical topology definition and exploration
Interactive waveform viewer
Macro modelling support (DML)
IBIS 5.0 support
IBIS ICM model support
Spectre-to-DML
HSPICE-to-IBIS
Lossy transmission lines
Coupled (3 net) simulation
Differential pair exploration and simulation
AUTOROUTER Standard Professional Designer
6 Signal Layers at a time (no board layer limit or pin limit)
Shape-based or Gridded routing
SMD Fanout
Physical Trace Width by Net and Net Classes
45-degree / Memory Pattern Routing
Interactive Routing with Shoving and Plowing
Interactive Floorplanning
Online Design Rule Checking
Flip, Rotate, Align, Push, and Move Components
Placement Density Analysis
Min/Max, matched length rules based autorouting
Pin-pair rules, Area rules based autorouting
Crosstalk controls, parallelism rules based autorouting
Differential Pair Autorouting, Automatic net shielding
High-speed rules-based autorouting
256 signal layer limit OrCAD AI Option PCB AutoRouting Option
DFM rules-based autorouting automatic trace spreading, via reduction and mitering PCB AutoRouting Option
Spacing Net Class - Class Rules PCB AutoRouting Option
Via Rules by Net and Net Class PCB AutoRouting Option
Mircovia features including Plural and Stacked microvias PCB AutoRouting Option
Auto Test Point Generation and Clearance Rules PCB AutoRouting Option
Layer-specific rules-based autorouting PCB AutoRouting Option