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Sigrity System SI

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Cadence® Sigrity SystemSI technology addresses high-speed design challenges with comprehensive chip-to-chip signal integrity (SI) analysis solutions. Sigrity SystemSI is available in two configurations: Sigrity SystemSI Parallel Bus Analysis targets source-synchronous designs, and Sigrity SystemSI Serial Link Analysis focuses on projects with SerDes channels.

Sigrity SystemSI includes a block-based schematic editor to make it easy to get started with very basic data. As design work progresses, models are swapped in to reflect the detail of design structures. Sigrity SystemSI includes frequency domain, time domain, and statistical analysis methods to ensure robust parallel bus and serial link interface implementations.

 

Features

 

Sigrity System Explorer
This general-purpose topology exploration tool is perfect for exploring end-to-end signal and power topologies. Signal integrity or transient power integrity analysis can be performed. This unique solution blends the features of standard topology exploration tools with the ability to analyze signal and power together. Complex interconnect models can be included and connected to a single driver/receiver/discreet symbol that automatically replicates the circuit for each of the ports on the interconnect model.

Sigrity SystemSI Parallel Bus Analysis
This end-to-end analysis solution targets source-synchronous parallel interfaces such as designs with DDRx memory. Pre-layout capabilities (including an optional via wizard) enable work to begin with models that are quickly generated and connected. As the design is refined, more detailed models are swapped in to reflect actual hardware behavior. Concurrent simulation accounts for the effects of dielectric and conductor losses, reflections, inter-symbol interference (ISI), crosstalk, and simultaneous switching noise. These simulations are able to fully account for impacts associated with non-ideal power delivery system characteristics. Graphical outputs and post-processing options give designers insight that enables rapid system improvements.

Sigrity SystemSI Serial Link Analysis
This award-winning chip-to-chip analysis solution focuses on high-speed SerDes designs such as PCI Express® (PCIe®), HDMI, SFP+, Xaui, Infiniband, SAS, SATA, USB, and more. It makes early assessments using basic templates. Support for industry-standard IBIS AMI transmitter and receiver models enables simulations of channel behavior for serial links with chips from multiple suppliers. Chip model developers have access to techniques that assist them in model development. Models of multiple packages, connectors, and boards can be added to reflect the entire channel. Simulations identify crosstalk issues and show the effectiveness of chip-level clock and data recovery (CDR) techniques. Full-channel simulations including millions of bits of data confirm overall bit-error rate (BER) to determine if jitter and noise levels are within specified tolerances.

Creation of IBIS-AMI models is offered through a wizard-based methodology. Both TX and RX models can be created using industry-proven equalization algorithms that are used by the Cadence Design IP SerDes PHY teams to create IBIS-AMI models for their products. The IBIS-AMI building technology provides an automated methodology for combining, parameterizing, and compiling the algorithms into an executable model. Customized code can be included if so desired. Depending on product licensing, the created models will be either tool independent or be restricted to run only with Sigrity tools such as Sigrity SystemSI technology.

 
Benefits
  • Fast and precise simulations for designs at frequencies that range from DC to 10+GHz
  • Accurate handling of non-ideal power delivery system influences on SI, which can be the dominant cause of reliability problems
  • Easy-to-use graphic editor including a novel net-based, block-wise schematic editor
  • Proven S-parameter handling to ensure accurate system-level time domain simulations
  • Related Cadence tools support model extraction, tuning, conversion, and hook-up
  • SPICE subcircuit-based modeling approach supporting common formats such as IBIS, HSPICE, Touchstone, BNP, and MCP
  • Highly automated measurement and reporting capabilities

Parallel Systems has produced over 300 free tutorials for you

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