"Designed with OrCAD of course!"
Ryan Dunwoody - Pi-Top
“With Allegro TimingVision, the routing process has sped up dramatically, from four weeks, down to four days,”
Bill Munroe - Cavium
Designed with Cadence.
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“We’re very optimistic about our future with the scalable OrCAD PSpice and Allegro PCB Designer tools"
The Cadence solution reduces our PCB development time by 80 percent
- Gisbert Thomke, Group Leader, IBM R&D Lab
Designed with Cadence OrCAD and Allegro since 2003
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Cadence Customer Testimonials
The Cadence solution enables us to enter up to 99 percent of signals in table format, which, along with improved analytics and a unique integrated environment, reduces our PCB development time by 80 percent
- Gisbert Thomke, Group Leader, IBM R&D Lab
The Cadence Allegro system interconnect design platform has significantly changed our high-speed board design process. Our partnership with Cadence has allowed us to decrease our time to market and increase our confidence in first pass success for our designs. Projects that used to take quarters to complete now take only months, and we trust that the first spins will come back functioning as intended.
- Tim Kent, Vice President of Engineering, Liquid Computing Corp. TESTIMONIAL PDF
During the design of the GS0036, we at Gnodal found the new Design Replicate feature in Allegro helped to considerably reduce our timescales. Initially we were able to use the feature to reproduce placements of similar circuits from previous designs in our placement studies. We then used it to very easily repeat the placement and routing of complex circuits and finally it allowed us to have more than one layout engineer working on the design simultaneously. This feature has helped Gnodal target an aggressive timescale on an important design.
- Jim Corke - Gnodal
As a designer I have used similar features in medium to high end CAD systems before with some level of success. With this powerful enhancement to the routing functionality, Cadence have managed to up the game and take PCB design to next level of evolution. I can see myself using these key features a lot within our forthcoming designs and of course ultimately, it will save us a lot of time and effort into getting what we want done quickly and effectively.
Joe Kotvics Acano. WATCH VIDEO
If you ever need a reference from a small customer, I am very happy to vouch for the professionalism of your team. I am really happy with the way your team managed the whole process of selling the OrCAD suite to me, I just wish to express my thanks
- Florin Stroiescu - Strasmax
As a result of using the OrCAD solutions for PCB development, "home2net" has achieved a 30% faster development cycle, has reduced costs by 15%, and can readily meet its stringent timeto-market goals. - Home2Net Success Story
"The majority of our PCB layouts are complex, highly constrained designs that demand a signal integrity-based design-flow. The Cadence Allegro v16 schematic entry, PCB layout and SI analysis tools, provided through Parallel-Systems, give us the ability to handle the most challenging designs and maximise our competitive edge. Continual feature development, expert technical support and a high level of productivity are just three reasons why weve built our company around Cadence Allegro."
- Chris Halford, Advanced Layout Solutions
We chose PSpice for several reasons. The availability and selection of models is vast and updated online. Time saving features like the Checkpoint Restart allows me to store simulation states at various time-points and then restart simulations from any of the simulation states. All in all its a great product and is a key part of our design team. I can see why it is the industry standard
- Paul Overton - Senior Electrical Engineer - Viper Subsea
With an integrated tool flow in Cadence Allegro, we have seen increased productivity for PCB design. Now that our designs are heavily constrained, the PCB design might be expected to take a lot longer. However, the design checking process is so much shorter, that the overall time is less. More importantly, with all the necessary nets constrained in the schematic, the chances of a PCB revision for signal integrity reasons have been vastly Reduced. Cadence Allegro design entry HDL has had advanced features (such as constraint editor) for a long time, and it has been stable for us. We have not seen any bugs with the software. This compares favourably with our experience with competitive tools which promised good things, but in VMETROs experience were not stable.
- Hugh Tarver Engineering manager at VMETRO Ltd.
Cadence Allegro has helped us push the technological envelope for designing layouts using multi site BGA, high density, RF, digital and high layer counts. As a leader in ATE hardware fixtures, we have found the alliance between Cadence and Parallel Systems a useful synergy, where both companies have given their expert advice towards new software tools, updates and training programmes, helping us to make sure that we keep ahead of our game.
- Nigel Rowe Shane Consultants Limited
I am thoroughly impressed with the Orcad Unison package as a whole; the software has proved to cater for all my demands as a design engineer. Complex and large-scale schematics are easily realised and intuitively managed. The integration between the PCB layout and the schematic is seamless and enormously simplifies the development process. The SPECCTRA PCB auto-router is both powerful and simple to use. This has resulted in a faster time to market compared with previous software packages.
- ZaferJarrah - Hybrid Instruments UK
OrCAD PCB Designer with PSpice provides my business with an integrated development tool that works from the first schematic concept, through simulation and on to product realisation - all straight out of the box. It's even useful during hardware debug as the link between the Capture and PCB Designer allows for quick and easy track tracing. Add in the effective and intelligent customer support and you have a first class package. OrCAD Capture allows me to get on with the job of designing electronics without having to fight my software. From jobs with 10 components on a single sheet through to complex hierarchical systems with 30 schematic pages, Capture has handled it all
- Craig Britton Supply Design
We purchased OrCAD Layout and it was good value for money. We felt that it was not meeting the requirements for todays high speed technology and complex designs, and were pleased to hear that the product was to be upgraded. The new, OrCAD PCB Designer utilises the highly regarded Allegro PCB Design Editor which has brought greater efficiency in component placement and routing; we were very impressed with the way it handled routing in planes/copper pouring etc. Library management is significantly improved and there is a general feeling of increased productivity. It is fully compatible with the high end Allegro product range
Jim Hurford. Dayford Designs.
OrCAD PCB Designer is a great tool for a service bureau like us. With PCB Designer, we can use OrCAD Capture, the popular schematic entry tool used by many of our customers. We also do PCB layout based on the solid Allegro database format. This allows us to reuse designs, if necessary, and addresses high-speed issues within the Allegro Environment.
- Ronald Weber, PCB designer at DesConTec
Bayside Design Inc Read Full story »
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Liquid Computing Corporation Read Full story »
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Veri Silicon Read Full story »
Chris Menkus Founder and CEO, City Semiconductor Chris Menkus, outlines the benefits of using the solid support and collaboration technology found in Cadence Hosted Design Solutions’ environment to create their new high speed 12 bit Analog to Digital Converter.
Angela Liang Freescale Semiconductor Hear from Angela Liang, Sr. Mixed-Signal Verification Engineer, at Freescale Semiconductor as she describes how they utilized the Cadence Low Power and Mixed-Signal Solution to verify the company’s Kinetis Microcontroller products targeted for automotive and internet-of-things applications.
Michael Schinzler Freescale Semiconductor Hear from Michael Schinzler, Logic Designer at Freescale Semiconductor, as he highlights the use of the Cadence Rapid Prototyping Platform to help verify their e6500 Power Architecture Core.
S3 Flavio Cali Hear from Flavio Cali with S3 Group, as he highlights the user experience of Cadence Physical Verification System (PVS) for SoC design.
ARM and Cadence Collaboration
William Orme, ARM and Steve Brown, Cadence ARM and Cadence Collaboration Hear from William Orme, Strategic Marketing Manager at ARM, and Steve Brown, Director of Product Marketing at Cadence, as they describe the collaboration and use of the Cadence Interconnect Workbench with ARM’s CoreLink System IP to help SoC designers achieve their power, performance and area goals.
AMD Bryan Sniderman, Verification Architect for AMD, introduces the UVM Multilanguage (ML) Open Architecture to simplify verification IP (VIP) reuse.
Vahid Ordoubadian Broadcom Vahid Ordoubadian, Director - Mobile Platform Group at Broadcom, describes the use of Cadence Palladium XP to validate a new architecture for a complex mobile SoC for mobile platform devices.
ARM, Samsung and Cadence
ARM, Samsung and Cadence Dipesh Patel, EVP and GM, Physical IP Division at ARM, Ana Hunter, VP of Foundry at Samsung Semiconductor and Chi-Ping Hsu, SVP, R&D at Cadence discuss the collaboration between the three companies to develop the first 14nm, FinFET implementation of the ARM Cortex A7.
Rohit Pandharipande Analog Devices Rohit Pandharipande, Design Engineer at Analog Devices, details working with Cadence migrating from VMM to the UVM Compliant, Cadence Verification IP (VIP) to verify a Dynamic Memory Controller.
Kavitha Nagarajan Open-Silicon, Inc. Kavitha Nagarajan, Lead Engineer – IC Package Design at Open-Silicon, Inc., describes how the company leveraged the Cadence Integrated SPB environment to successfully complete a complex project with a tight deadline.
Shrikrishna Mehetre and Souvik Mazmunder Open-Silicon, Inc. Hear from Shrikrishna Mehetre and Souvik Mazmunder, with Open-Silicon, Inc., as they highlight the use of Cadence Encounter digital RTL-to-signoff products to achieve 2.2 GHz performance on a 28nm ARM Dual-Core Cortex-A9 processor.
Abhishek Jain STMicroelectronics Abhishek Jain, Technical Manager at STMicroelectronics, talks about working with the Cadence Incisive Verification Solution to deploy a UVM multi-language, low-power verification methodology resulting in earlier and integrated verification.
Antoine Dejonghe Program Manager imec Antoine Dejonghe, Green Radio Program Manager at imec, highlights the use of the Cadence CPF-Driven Advanced Low-Power Solution that accelerates the company’s next generation 4G wireless designs.
David Murray Duolog David Murray, CTO at Duolog, discusses collaborating with Cadence to help customers address SoC integration and verification.
Angelo Consoli Saphyrion Angelo Consoli, Managing Director at Saphyrion, details how they leverage the Cadence Virtuoso custom/analog flow and design services to develop ASICs High-End ground and space applications.
Marleen Boonen and Vladislav Palfi Methods2Business Listen to Marleen Boonen and Vladislav Palfi, from Methods2Business, as they describe how they use the Cadence Virtual Platform and Verum’s Analytical Software Design solution tool to debug earlier in the design cycle and ultimately design software faster and more efficiently.
Romain Feuillette STMicroelectronics Romain Feuillette, Team Leader at STMicroelectronics, talks about succeeding with the Cadence innovative Virtuoso custom/analog flow to meet aggressive roadmaps and improve productivity at all process nodes.
Dermot Barry S3 Dermot Barry, VP – Silicon Business Unit at S3, highlights how they leverage Cadence mixed-signal solutions to help their customers achieve business success through fast time to market and first time right silicon with the optimized power, performance and area.
Imperas and Cadence Collaboration
Larry Lapides, Imperas and Larry Melling, Cadence Imperas and Cadence Collaboration Hear from Larry Lapides, Vice President of Sales at Imperas, and Larry Melling Product Manager - Virtual System Platform at Cadence, as they describe the collaboration and use of the Cadence Virtual System Platform along with Imperas’ processor models and verification analysis and profiling tools to address challenges of embedded software development for complex SOCs.
X-Fab Dr. Jens Kosch Chief Technology Officer Dr. Jens Kosch, CTO at X-Fab, highlights the use of the Cadence Mixed-Signal solution to help mutual customers with their designs.
imec Luc Van de hove President and CEO Luc Van de hove, President and CEO at imec, details imec's business focus and highlights the collaboration between imec and Cadence.
Francois Lemery STMicroelectronics DAC 2012 presentation – ST 20nm Constraint Driven Modgen Flow
IBM Nancy Pratt Nancy Pratt, BIST Verification Lead at IBM, details the use of Cadence Verification tools to help streamline and provide more detailed reports, improve planning and increase scheduled adherence.
LeCroy John Wiedemeier John Wiedemeier, Product Marketing Manager – Protocol Solutions Group at LeCroy, describes the collaboration with Cadence utilizing PCI Express 3.0 to help mutual customers reduce development risk, improved system interoperability and reduce time to market.
Xilinx David Beal David Beal, Zynq 7000 EPP Product Manager at Xilinx, describes how the Cadence Virtual System Platform helps to accelerate product development
Freescale Semiconductor Wai-Chee Wong Wai-Chee Wong, Senior Member of Technical Staff at Freescale Semiconductor, details how Palladium XP helps speed their verification effort by 10,000x over simulation.
Narendra Konda NVIDIA Narendra Konda, Director, HW Engineering at NVIDIA, discusses leveraging Palladium XP and the Rapid Prototyping Platform to integrate complex hardware and software designs.
AMD Alex Starr Alex Starr, Hardware Emulation Architect at AMD, highlights the unique capabilities of Palladium XP and in-circuit acceleration
Luigi Capodieci GLOBALFOUNDRIES Luigi Capodieci, Director of Design for Manufacturing, R&D Fellow at GLOBALFOUNDRIES, discusses how they collaborated with Cadence on pattern-matching technologies to accelerate full-chip DFM signoff.
Ashok Mehta TSMC Ashok Mehta, Sr. Manager System Verification/Software Architecture describes how they worked with Cadence to Address System-Level Complexity with the TSMC ESL Reference Flow 12.
Lars Liebman IBM Lars Liebman, Distinguished Engineer at IBM, highlights the collaboration between IBM and Cadence in solving design challenges at 20nm and 14nm technology nodes.
Anis Jarrar Freescale Semiconductor Anis Jarrar, Principal Design Engineer, at Freescale Semiconductor describes how they utilized the Cadence Low-Power Solution to design and implement the complex Kinetis SoC.
Silicon Blue Technologies
Andrew Chan Silicon Blue Technologies Andy Chan, Vice President of Engineering at Silicon Blue Technologies details how they utilize the TSMC-certified Cadence DFM Services along with Cadence technologies to develop consumer mobile applications.
Larry Getman Xilinx Larry Getman, Vice President Processing Platform Marketing at Xilinx describes working with Cadence and the Virtual System Platform to developed the Zynq-7000, the industry's first virtual platform for system design and software development.
David Genzer BIOTRONIK David Genzer, Director of IC Development at BIOTRONIK describes how they leveraged the Cadence digital implementation and signoff flow and CPF-enabled low-power solution to help deliver the most advanced and sophisticated pacemaker product on the market.
Chris Day Ambarella Chris Day, VP Marketing and Business Development at Ambarella, details the collaboration between Cadence and Samsung that resulted in a first-time silicon successful 32nm HD digital camera SoC.
Global Unichip Corporation (GUC)
Alex Kuo Global Unichip Corporation (GUC) Alex Kou, Senior Design Manager at Global Unichip Corporation, highlights how the CPF enabled Cadence Low Power Solution helps them achieve 100+ low power design tape-outs and address their low power design challenges in future technology nodes.
Ana Hunter Samsung Ana Hunter, Vice President of Foundry North America at Samsung describes how they use Cadence technology to address challenges at 20nm technology node.
Peter van Staa Bosch Peter van Staa, Vice President of Engineering at Bosch highlights how they improved design efficiency by 25% utilizing the Cadence Design Environment.
Fujitsu Semiconductor Europe GmbH
Raimund Soenning Fujitsu Semiconductor Europe GmbH Raimund Soenning, Manager at Fujitsu Semiconductor Europe GmbH describes how they leverage the Cadence functional verification methodology to help develop large SoCs in the automotive industry.
Thomas Riener austriamicrosystems Thomas Riener, Sr. VP, General Manager Foundry Business at austriamicrosystems describes how they leverage the Cadence unified custom/analog flow to design the company’s analog IC products.
Narendra Konda NVIDIA Narendra Konda, Director of Hardware Engineering at NVIDIA, outlines how the Cadence System Development Suite helps his design team successfully integrate complex hardware and software, develop app-ready systems more quickly, and ultimately improve the overall quality and competitiveness of their products.
Simon Davidmann Imperas Software Simon Davidmann, President and CEO of Imperas Software highlights how the partnership with Cadence, leveraging the Cadence System Development Suite provides a solution to help make customers more efficient, save development costs and get products to market faster.
Ty Garibay Texas Instruments Ty Garibay, Director of IC Engineering for OMAP platform business unit at Texas Instruments describes how they leveraged Cadence unified digital flow to develop SoCs for mobile applications productively, profitably, and quickly.
Romain Feuillette STMicroelectronics Romain Feuillette, Team Leader at STMicroelectronics describes the benefits of using the Cadence Virtuoso-based custom/analog flow to enable faster time to market, higher productivity, and product innovation.
Ross Teggatz Triune Systems Ross Teggatz, President/Founder at Triune Systems outlines the values of using the Cadence unified digital and unified custom/analog flows to meet their mixed-signal design requirements and close time to market gaps.
Global Unichip Corporation (GUC)
Albert Li Global Unichip Corporation (GUC) Albert Li, Director of Design and Development at Global Unichip Corporation, outlines the benefits of partnering with Cadence for giga-gate/GHz, 28nm design.
Martin Spohr Renesas Martin Spohr, Principal Design Engineer Design Services at Renesas Electronics Europe describes the benefits of using the Cadence Encounter Digital Implementation System post assembly closure methodology to ensure design closure on their complex giga-gate design.
Niall O hEarcain Silansys Semiconductor Niall O hEarcain, the CEO of Silansys Semiconductor describes the benefits of partnering with Cadence for advanced RF level and multimillion-gate designs.
Li-Fu Chang SMIC Li-Fu Chang, SoC Technology Development Director at SMIC describes the joint effort of SMIC with Cadence in creating DFM-clean libraries and accurate IP, CMP, and litho models for their worldwide customer base.
James Wei NextIO James Wei, Director ASIC Development at NextIO, discribes the benefits of using Cadence Services to reduce risk and meet schedule targets accurately and predictably.
Frank Ferro Sonics Frank Ferro, Director of Marketing, describes the success with the Cadence Encounter Digital Implementation System.
Applied Micro Circuits
Sumbal Rafiq Applied Micro Circuits Sumbal Rafiq, Director of Engineering at Applied Micro Circuits, describes the success with the Cadence Encounter Digital Implementation System.
Greg Bodi Nvidia Greg Bodi, System Design Senior Manger at Nvidia talks about Allegro PCB products.
Jarie Bolander Tagent Jarie Bolander, Tagent Co-Founder and Vice President of R&D talks about how Cadence Hosted Design Solutions and Services helped Tagent develop the first-ever Antenna on Chip.
Tim Richardson Micro Linear Tim Richardson, CEO of Micro Linear talks about how Micro Linear and Cadence collaborate on world's first 1.9-gigahertz RF transceiver IC with a fully integrated power amplifier, the ML1900.
Dan Dobberpuhl P.A. Semi Dan Dobberpuhl, President and CEO of P.A. Semi talks about using the Encounter platform to overcome high-performance, 65nm design design challenges.
Toby Farrand Digeo Toby Farrand, Chief Technical Officer of Digeo talks about how Digeo and Cadence Engineerings Services collaborate to achieve first silicon success on X-Stream project.
Douglas Pattullo austriamicrosystems Douglas Pattullo talks about how the robust and stable technologies from the Virtuoso custom design platform help austriamicrosystems build design kits that facilitate fast, productive design to market.
Bob Bridge Zilker Labs Bob Bridge, CEO of Zilker Labs talks how Zilker Labs and Cadence merge power management and power conversion into the ZL 2005 IC.
Tom Rudwick Intrinsity Tom Rudwick of Intrinsity talks about how the Virtuoso accelerated layout technologies, with its easy-to-use shape-based router, help Intrinsity to meet electromigration constraints and design to volume.
Ken Rousseau Virage Logic Ken Rousseau, VP Software Development of Virage Logic talks about how Virage Logic delivers memory compiler using high-performance, industry-standard Virtuoso custom IC layout.
Doug Shute Bitwave Doug Shute, CEO of Bitwave Semiconductor talks about how Bitwave and Cadence combine to develop software-defined radio.
Eric Broockman Alereon, Inc. Eric Broockman, CEO from Alereon, Inc. and Cadence partner to design the world's highest performance ultrawideband chipset.
John Glossner Sandbridge John Glossner, CTO of Sandbridge Technologies talks how Sandbridge and Cadence set out to revolutionize mobile handsets with a multi-threaded DSP architecture.
Laurent Mailet-Contoz STMicroelectronics Laurent Mailet-Contoz, Project Leader from STMicroelectronics uses the Incisive verification platform at the transaction level to reduce their design cycle and help the company to be the first to new markets.
Amit Chandra P.A. Semi Amit Chandra, Sr. Engineering Manager of P.A. Semi talks about using the Encounter platform to overcome high-performance, low power design challenges.
Bruce Cory nVidia Bruce Cory, DFT Methodology Manager from nVidia talks about the importance of test coverage and how Cadence Encounter Test delivered quality in several situations.
Chris Malachowsky NVIDIA Chris Malachowsky, VP of Engineering from NVIDIA talks about the challenges of dealing with 90 and 65 nanometer technologies, and how Cadence technologies and partnering approach help NVIDIA get results.
Martin Spohr NEC video Martin Spohr, Senior Engineer, NEC Electronics from NEC Video talks about using Encounter Conformal Constraint Designer to overcome nanometer design challenges.
Thilo von Selchow ZMD Thilo von Selchow, CEO from ZMD talks about how ZMD and Cadence Engineering Services work together to produce cutting-edge ZigBee wireless solutions.
TSMC North America
David Lan TSMC David Lan, Senior Manager, Design Methodology from TSMC North America collaborates with Cadence to offer 90-nanometer design solutions to its customers.
Chris Silsby Agilent Technologies Chris Silsby from Agilent Technologies talks about how the Virtuoso accelerated layout technologies help Agilent complete a variety of experiments in hours instead of weeks, and complete the project on schedule.
Edwin Li Zeevo Edwin Li, Ph.D. from Zeevo talks about how the Virtuoso custom design platforms speeds the design of highly integrated Bluetooth SoC RF modules by enabling simulation of designs at real-time 2.4-gigahertz speed through the Virtuoso AMS Designer Simulator.
Steve Stern Sipex Steve Stern from Sipex talks about how the Virtuoso custom design platform and Cadence Engineering Services provided technologies and methodologies that reduced design cycle time from months to weeks and increased employee retention.
Jai Kumar Sun Microsystems Jai Kumar, Verification Technologist from Sun Microsystems shared his verification experience of advanced development of UltraSPARC processors with Cadence Incisive Xtreme series.