Adding Part References

PCB designs are flat and, as a consequence, every part in the Design must have a unique Part Reference. This can be added as Parts are Placed if the “Automatically Reference Placed Parts” preference is set in the Miscellaneous Preferences, or manually after the Parts have been placed by editing the Part Reference text property, or automatically after the Parts have been placed with the Tools>Annotate function.

(Note that PSpice is inherently hierarchical and is able to handle hierarchical designs where there may be repeated references)

Part References consist of a Prefix, determined from the Package Properties for the Library Part followed by a sequence number, typically starting from 1.

Tools>Annotate modes are: Incremental, the Part References in the design are scanned to determine the last used sequence number for each Part Reference Prefix and then any parts with a “?” Part Reference will be annotated from the last used sequence number for that Part Number Prefix, note that this process does not “correct” any annotation issues with any already referenced parts; Unconditional, re-annotates the entire design starting from the top left of the first Schematic Page through to the bottom right of the last Schematic Page in the design, this should not be used once there has been a netlist loaded into a PCB since the Part References are one of the primary connections between the Schematic and PCB designs.

Tools>Annotate can also number the Pages and Page Count in the Title Block properties for multi-sheet designs.

Design Rule Checking

Design Rules checking, checks the design against a number of rules for “correctness”. Since some of these rules may be permissible in certain designs, markers for Design Rule Checks, once added, can be waived to prevent them being reported.

The 17.4 Release introduces Online DRC checking, View>Others>Online DRCs if the window isn’t visible. This window dynamically lists any design rule violations that have been configured for “online”, rather than “batch”, checking in PCB>Design Rules Check>Rules Setup. A double-click on an entry in the Online DRCs list will highlight the DRC object in the Schematic Page.

Use PCB>Design Rules Check to configure the Design Rule Checking and run the “batch” design rule checks. 

Creating DRC Markers for warnings can be useful since the DRC Markers can be “browsed” from Edit>Browse>DRC Markers, which displays a summary list of all of the DRC Markers, and a double-click on one of the DRCs listed in the summary will navigate to the DRC Marker in the Schematic. Even though some of the DRC markers may be warnings, it’s worth checking what they are rather than just accepting them.

Some of the checks are not applicable to all designs, for example: in Physical Rules, “Check Power / Ground short” is designed for a specific application which few users would require.

The ERC Matrix checks Pin and Port Type to Pin and Port Type for any potential violations. The “cells” for the matrix have three states: Grey, “do nothing”; Yellow W, issue a warning; Red E, issue an error. Left-clicking in the “cells” will cycle through the three possible values. Read the matrix as “type in the left column” TO “type across the diagonal”, for example, with the default settings: “Input” to “Input”, “do nothing”; “Bidirectional” to “Input”, do nothing; “Bidirectional” to “Bidirectional”, do nothing; “Output” to “Input”, do nothing; “Output” to “Bidirectional”, issue a warning – since the Bidirectional might be driving; “Output” to “Output”, issue an error – since both drive. And so on.

By default, warnings are only issued for Unconnected Input Pins and Input Ports. Some users like to get a warning for “any” unconnected Pin or Port, in the design, toggle the Grey “cells” to Yellow W for the Unconnected row in the ERC Matrix if this is a requirement.

Creating a Netlist

Tools>Create>Netlist open the netlisting form. Use the PCB tab to for the settings to create a netlist for OrCAD PCB Editor. Note that the netlist files get created in an allegro sub-folder, which is the recommended approach to keep the PCB related data separate from the schematic related data.

Even though this is only a partial design at this stage, it is still possible to create a netlist.

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