Creating designs with digital components is no different from creating designs with analog components, Place>Part, Place>Wire, and so on.

Differences with simulating digital designs

Where digital simulations do differ though is that the simulations results are in the form of “state” rather than voltage so there are some specific parts to support this. Parts are modelled with digital primitives for buffers, inverters, flip-flops, logic blocks, pin delay devices and I/O models, which greatly speed up simulations compared to using transistor level models.

There are symbols for HI and LO in the sources.olb and pull-up and pull-down parts in the dig_misc.olb to avoid the use of analog resistors. There are sources for digital clocks and other stimuli.

Supply Voltages are common for the digital components.

Many of the outputs can be left “open” without any simulation issues.

Transient analysis is the only basic analysis that can be performed on a digital circuit.

By default, any flip-flops won’t get initialised so they will have a state of X, unknown, and this will “ripple through” the design causing most, if not all, nodes to be unknown. In the simulation profile, the gate level simulation options can be changed to set all of the flip-flops to a known 0, or 1, state for the purposes of simulation but “real” designs should implement some form of “master” reset.

Results in the Probe window will reflect the state of the nodes in the circuit: solid green lines for stable 0 or 1; double red lines for X (unknown); double yellow lines between states for rising and falling transitions; triple blue lines for tri-state. It is also possible to view the nodes as buses in the Probe window, formatted as hexadecimal (default), or binary, or octal, or decimal. If there is insufficient space to display the bus values, the values will be displayed as *, or just transitions if the displayed value is compressed enough.

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