What are Rules (Constraints)?

Rules, or Constraints in PCB Editor, control the details of the Board design as it is created to ensure that the design meets certain requirements. These requirements may be determined by what can be manufactured, usually specified by the PCB fabricator for their manufacturing capability, how small a track, or gap between tracks, can be, or may be, determined by some electrical requirements like impedance, or spacing of sensitive and higher voltage, connections.

The Constraint Manager

Constraints in PCB Editor are configured in the Constraint Manager. The Constraint Manager window has Domains on the left-hand side and within those domains are Workbooks and Worksheets. Domains are: Electrical, Physical, Spacing, Same Net Spacing, Manufacturing, Properties and DRCs. Workbooks contain categories of settings and the Worksheets contain the settings and details of the values. Since resolving some DRCs may involve changes to the Constraint settings, it is convenient to be able to review DRCs from within the Constraint Manager window without having to switch back to the PCB Editor window.

Note that changes cannot be made to the Constraint Manager settings if the PCB Editor session that it is connected to is running an active command.

Physical Rules

Physical Rules relate to the parameters of track that is added to make connections in the Board.

The Min Line Width specifies the track width that will be used as a default when connections are added and the Max Line Width, if set, specifies the maximum width of track that can be added without a DRC being reported. A value of 0 for the Max Line Width means that this will not be checked and “any” width, larger that the Min Line Width, will be acceptable.

The Min Neck Width specifies what the track width can be set to for restricted areas, for example, to get between Pins or to get wider, Power for example, tracks onto smaller pins. The length of the Neck Width can be used for is set by the Max Neck Length, and this will typically be of the order of 1-2 mm to restrict using the Neck Width for the entire connection. A Max Neck Length of 0 will result in a DRC if any use is made of the “necked” width when making connections.

The Differential Pair coupling parameters set the spacing and tolerance for Differential Pairs, see this note:  https://www.parallel-systems.co.uk/wp-content/uploads/2020/02/diffpair_definition.pdf for a comprehensive discussion of defining Differential Pair parameters.

Vias used to change layers when making connections are selected from the Vias cell, any Padstack configured in the Board database, or libraries, may be selected. Note that all Padstacks are listed, including single layer Padstacks that would not be suitable for making connections.

PCB Editor supports Blind and Buried Vias for all license levels and the Blind / Buried Via Stagger defines the amount by which they are offset. Only the Minimum Stagger is checked by default.

Allow Pad-Pad Connect is enabled by default so overlapping Pins and Vias are permitted, set the required option from the drop-down to restrict, or prevent entirely, overlapping Pins and Vias.

Allow Etch controls which layers connections can be made on. By default, all layers are enabled.

Allow T’s controls where T connections can be made. The default setting of “Anywhere” is not restrictive but this can be restricted by selecting an alternative setting from the drop-down.

Spacing Rules

Spacing Rules relate to the air gap between object types on different Nets in the design: Line, Thru Pin, SMD Pin, Test Pin, Thru Via, BB Via, Test Via, Shape, Bond Finger (not applicable to OrCAD PCB Editor) and Hole (where unused internal pads have been suppressed). This results in a large number of settings to cover every object type against every other object type.

The “right pointing triangle” in the column heading indicates that some details are hidden and only the “All” value will be displayed”, double-click in the column heading to display the details. If the “All” value has “***” in the value then the values in the parameters differ, if the “All” value contains a number, all of the parameters have that same numerical value for that category.

Same Net Spacing Rules

Same Net Spacing Rules relate to spacing between object types on the same Net in the design and control other rules beyond the air gap – since objects on the same Net would be unlikely to have a complete isolation air gap between them. A specific example is Shape to Pin which controls the amount that a Shape is cleared around a Pin when a thermal relief is formed.

Organising Rules and Nets

Rules can be defined in Constraint Sets for the Physical, Spacing and Same Net Spacing domains. There is always a predefined “Default” Constraint Set applied for each domain. Values in the “Default” Constraint Set can be changed. As many Constraint Sets as required can be defined to specify different values.

Nets can be organised into Net Classes, basically, those having a similar purpose in the design. A Constraint Set can then be applied to the Net Class so that any changes to the Constraint Set will be applied to all the Nets in the Net Class. It is also possible to assign a Constraint Set to individual Nets and apply values directly to Nets, overriding the applied values. Overriding values on individual Nets might be appropriate if the design only contains a few Nets but, for most designs, organising the Nets into Net Classes and applying a Constraint Set to the Net Class is a better approach.

Net Class – Class

When Nets in two Net Classes meet the “Default” Spacing values will be applied. This might be appropriate for many designs but sensitive and higher voltage Nets in the design can mean that different Spacing rules need to be applied. The Net Class – Class setup allows a different Spacing Constraint Set, or overrides (not preferred), to be applied and override the default spacing behaviour between two or more netclasses.

Labs

In the labs EITHER: use Labs 7-1, 7-2 and 7-3, setting Constraints within PCB Editor, OR: use Labs 7-1a, 7-2a and 7-3a, setting Constraints within OrCAD Capture, there is no need to work through both sets of labs for the Constraint Manager.

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