slidercavium777“With Allegro TimingVision, the routing process has sped up dramatically, from four weeks, down to four days,” Bill Munroe - Cavium sliderrasp777Designed with Cadence. Download design files here... slidersssl777“We’re very optimistic about our future with the scalable OrCAD PSpice and Allegro PCB Designer tools" slideribm777The Cadence solution reduces our PCB development time by 80 percent - Gisbert Thomke, Group Leader, IBM R&D Lab Short Term Rental OrCAD Switch3DbannerShort Term Rental OrCAD Cubessk1orcadx banner Parallel Systems Suite 1 and Suite 2 comparison FEATURES SUITE 1 SUITE 2 Floating Networked License 12 Months Maintenance Support Included In Purchase Price SCHEMATIC ENTRY + DATA MANAGEMENT Flexible Window layout Graphical, flat and hierarchical page editor and Picture block hierarchy OrCAD PSpice AD Basic - Restricted Capacity - see PSpice Matrix below Net Groups - Complex bus definition AutoWire 44,000 Schematic symbols Coloured Components / nets Tcl TK scripting support Online design rule check including custom DRC capability and Waive DRC Forward and back-annotation of properties / pin-and-gate swaps Schematic Part and Library editor Cross-probing and cross-placing FPGA design-in / pin import & export Multiple PCB netlist interfaces - New Design Sync for Cadence Flow Part Search Providers UltraLibrarian and Samacsys (Symbol, Footprint 3d Step Model) Property editor for pins, components, nets OrCAD SigXplorer SI Analysis Intelligent PDF creation Advanced Annotation Design Compare (detail and Graphical) Default Demo designs Extended Preferences Export ISCF (Intel Schematic Connectivity Format) Export / Import XML Altium Importer Schematic (PCB also available) Eagle Importer Schematic (PCB also available) Constraint Manager Component Information System Windows ODBC compatible format Interface to relational database and management systems Database query for part selection and parametric properties Schematic and BOM Variants Manager (Parts not Fitted and more). Component Information Portal (CIP), Access to Mouser, Digikey, Future, Farnell PCB EDITOR Spacing, Same net, Netclass and Class to Class rules Physical Constraint Rules DesignTrue DFM Wizard Design for Test Checks Design For Assembly Checks Design For Fabrication Checks Component Lead Editor Import File Manager DFM Pad Entry / Exit Rules Dynamic pad suppression / Unused Pad removal Cross Section Editor Padstack Editor IPC2581 Compliant Application Mode (General, Etch, Placement) Application Mode (shape) Full Skill Support Customisable Visibility Pane Dynamic Shape Pin Connection By Layer (Global/Shape/Pin/Layer) Dynamic Cross Hatch Shapes Dynamic Shapes (dynamic copper pours) Plow and Heal Move with autoroute adjust (Slide) Multiple placement options, manual, quickplace, auto and room Alignment x and y for components and modules Dynamic rat suppression Fan-out generators Interactive Routing using Working Layer (layer selection popup) Group route Bus Route and via patterns Line Fattening Differential Pair Static Phase Control rules Differential Pairs Physical rules and routing Blind Buried Single Click multiple via instantiation Push, Shove and Hug interactive editing Curve Routing Snake Routing for Hex pattern ICs Auto Finish (Route Completion Tool) Scribble Sketch Routing Route cleanup, optimization (Glossing) Embedded net names Split View Through Board Transparency (OpenGL) Flip Board Excellon NC Drill File export Gerber 274X, 274D artwork Output IPC2581 Import / Export Mentor ODB++ and universal viewer Impedance Calculator Interactive / Automatic Silkscreen generation Import Altium PCB (schematic also available) Import EAGLE PCB (schematic also available) Import PADS & PCAD Import IFF RF Shapes Import Export DXF Import Export IDF Export Intelligent PDF MCAD/ECAD Incremental design data exchange (IDX) 3D/2D Crossprobing STEP 3D Clash Detect STEP 3D viewer for selected item or complete PCB. STEP 3D Canvas Controls STEP 3D Import Export STEP 3D Canvas Highlight Selections Manual Design For Test (DFT) / Test Prep Associative Dimensioning Route Nets by Pick, 6- Metal Layers limit, no Pin Limit Route Automatic, 6- Signal Layers, no layer or Pin Limit Net Scheduling, T-Point rules (pin to T-point), T-Point definition Constraint Regions, region based rules (Rigid-Flex; BGA regions) Propagation delay rules (Relative) for nets or groups Propagation delay rules (Min/Max) for nets or groups Total Etch Length - Max/Min Length Extended (X)net rules Layer set rules Pin Pair rules Delay Tuning Dynamic Heads-up Display for critical rules Hug Contour routing (Flex) Segment over void detection Spread lines between voids Shape based curve fillet support, tapered traces Placement replication, template based design reuse Via array / Shielding - Shape and Trace based Rigid Flexi Zone Management Dynamic Zone Placement Inter Layer Checks for Rigid Flexi 3D Bending High Speed Analysis Impedance Workflow High Speed Analysis Coupling Workflow Placement Vision Route Vision Differential Pair Dynamic Phase Control rules Package Pin Delay (for die-2-die delay) rules Z-Axis delay feedback Backdrilling Automatic Design For Test (DFT) / Test Prep Panelization SIGNAL INTEGRITY Pre- & Post-route signal integrity analysis Pre Route Graphical topology definition and exploration Pre Route Interactive waveform viewer Pre Route Macro modelling support (DML) Pre Route IBIS 5.0 support Pre Route IBIS ICM model support Pre Route Spectre-to-DML Pre Route HSPICE-to-IBIS Pre Route Lossy transmission lines Pre Route Coupled (3 net) simulation Pre-Route Pre Route Differential pair exploration and simulation Pre Route PSpice SIMULATION Simulation capacity: 250 Nodes, 250 devices, 1M Transient, 10K AC / DC Sweep, limits Analog Devices: all except BSIM 3.3, BSIM4, Magnetic Core, IGBT, Tlines, DMI Analog behavioural modelling Digital Devices: All Learning PSpice Free Templates Bias Point, DC sweep, AC sweep and Transient analysis (with Temperature) Bias point voltages, currents and power display in Schematic Modelling Application in Capture Parametric Sweep Monte Carlo / Worst Case Check Point restart Auto Convergence, Advanced Convergence and Speed Mode Interactive waveform viewer and analyzer Waveform: FFT Advanced tools: FRA, Core loss PSpice video: Example Design Simple Circuit 1 PSpice video: Example Design Simple Circuit 2 PSpice video: Example Design Simple Circuit 3 PSpPice video: Example Design Simple Circuit 4 PSpice video: Example Design Simple Circuit 5 PSpice video: Example Design Simple Circuit 6 PSpice video: Example Design Simple Circuit 7
Floating Networked License