New features of OrCAD since V10.0 release...

OrCAD Capture - 17.2-2016

Please view the matrix to see which level the features appear in

  • Design Difference Viewer: New feature to perform logical and graphical comparisons between two designs, two schematic folders or two schematic pages and view the difference report in the form of a portable HTML format. (Watch Demo Video)
  • Advanced Annotation: The new advanced annotation feature lets users annotate multiple schematic pages at a time giving them complete control over their component annotation process in the design cycle. (Watch Demo Video)
  • Open Demo Design: The new Open Demo Design browser gives access to more than 150 demo designs made available from different locations, collated together to help users better understand Capture, Capture CIS and Capture _ PSpice Flow.
  • Export - Import XML: OrCAD Capture provides you the capability to convert Capture designs to XML format and vise-versa based on the requirement.
  • ISCF Export : Introducing direct ISCF (Intel Schematic Connectivity Format) feature for automating Intel-based design reviews to export hierarchical schematic designs in an Intel-approved format helping users optimize the design review process.
  • PDF Export: The new PDF export functionality lets users export Capture design as PDF file and provides intelligent design information.
  • Extended Preferences setup: The extended Preferences Setup window allows you to modify additional application settings in OrCAD Catpure like Command Shell, design and libraries, design rule check, CIS, NetGroup, NetList and Schematic.
 
OrCAD 16.6-2015 Release

Support for launching Lite in Licensed environment – Capture and all other OrCAD tools can be launched in the lite mode in licensed environment. The license selector dialog box provides the option to the user to select the lite mode for tool launch.

 
OrCAD Capture - 16.6 QIR#6
  • Windows 8.1 Support: OrCAD is officially supported on Windows 8.1
 
OrCAD Capture - 16.6 QIR#5(QIR #5 Factsheet)
  • Rapid PSpice Model Association: Capture now supports instance-level, PSpice model assignment directly to components in the schematic editor.
  • PSpice Library Search: Capture now provides an easy method to search through the installed library of simulation models / parts using PSpice Part Search.
  • Capture View-Only Mode: New view-only mode allows any project / schematic files to be opened for review without consuming a license.
  • Redefined Quick Place Menu: The Capture Place > PSpice Component menu has been updated with new items and sub-menus including; PSpice Ground, common discrete components, and new sources.
 
OrCAD Capture - 16.6 QIR#4
  • Display Properties Update: New display property option to display a value only if a value exists. Useful for commonly displayed properties like tolerance where you would not want to display the property name if a value does not exist.
  • Capture View only Mode: Allows Capture to be opened in read-only mode and does not check out a license. Accessible through command line switch capture.exe -viewer
  • Zero Pin Mechanical Parts: Mechanical parts with no pins like bar-codes, fiducials and mechanical holes can now be placed on the schematic and synced with the PCB
  • SI Flow Updates: The Capture SI flow now supports Sigrity products as well as OrCAD PCB SI
 
OrCAD Capture - 16.6 QIR#3
  • Object Alignment: Support for horizontal and vertical alignment of objects on a group or signal object level. New alignment toolbar added as well.
  • Object Distribution: Select and distribute objects evenly or horizontally.
  • Library Refresh: If libraries are updated outside Capture during an active session users can now perform a library refresh to display the updated information
  • Schematic Page Name Property in Titleblock: Titleblock now supports a new system property "Page Name". The "Page Name" property behaves like the "Schematic Name" property available in previous releases. Any change to the page name automatically synchronizes and updates the value of the property.
  • SI Flow Update (XNet View): Users can now easily view a filtered list of defined XNets in the current design. View provides data on the XNet included the flatnets that make up the XNets.
  • New NetGroup Display Options: Can now set NetGroup to display the definition of the NetGroup only if the name of the NetGroup is different from the NetGroup instance.
 
OrCAD Capture - 16.6 QIR#2
  • Common Property Text Justification:  You can now justify comment text and the text of displayed properties of any Capture object, such as Parts, Off Page Connectors, and Ports.
  • Tcl Updates: New Tcl scripting API updates are available for variant customized variables in the titleblock, visibility control on NetGroup alias, and access to project libraries.
  • Design Date Format Options: Two new options for data format display
  • Convert Views:  Convert Views supported in PCB Editor netlisting 
 
OrCAD Capture - 16.6
  • Capture – PCB SI Integration and Flow: With product integration comes a new bi-directional schematic entry/signal integrity flow that allows electrical engineers to explore circuit topologies, develop constraints, and analyze signal integrity. 
  • Quick-Place for Common Components: A new menu, Place >PSpice Component, enables quick-place for commonly used schematic or simulation components.  The menu items list of components is user-configurable and has been pre-populated with PSpice® simulation devices (passive, discrete, sources, digital).
  • User-Configurable Menus and Toolbars: Menus, toolbars, and icons in OrCAD Capture, PSpice Advanced Analysis, and Model Editor can now be customized. This makes it possible to run any Tcl method or script from the menus.
  • Enhancements to the Find Function: The Find function now allows searches for parts by value of a given property (e.g. Property Name=Value) or use of a regular expression as the search string. For example, to search for components with designators starting with C or R and followed by any number between 2 and 9, use the search string Part Reference=(C|R)[2-9].
  • NetGroup Enhancements: The NetGroup use model is now aligned with the Bus use model for intuitiveness and consistency. Enhancements areas include: assign a NetGroup to a Bus, reorder pins in an unnamed NetGroup, add and remove pins from a NetGroup, visible NetGroup references, and find NetGroup references.
  • Enhanced Save Function for Design and Library: Pages that are changed and need to be saved are now marked by an asterisk (*) in the Capture Project Manager. When a save is initiated, the marked pages are saved.
  • Global Replace for OffPage: The Find and Replace dialog box (Edit> Global Replace) has a new option, OffPage Connector, to find and replace OffPage connectors.
  • Preserve “User-Assigned” Designator: Reference designator management improvements now track the user-modified references and allow finer end-user control over managing the part references for the entire design. A reference designator can be interactively set as user-assigned through the newly added “User-Assigned” flag to preserve designators and references in conjunction with the Preserve Designator and Preserve User-Assigned Valid References in the Annotate window. Capture will also mark a reference designator as user-assigned if the reference is manually changed in Property Editor, manually changed in the schematic canvas, or changed by the board through back-annotation.
  • Design Level Auto Reference: In addition to schematic-level annotation, design-level annotation is now available by selecting the Design Level option in the Miscellaneous tab of the Preferences dialog box. An option to preserve references when copying is also available.
  • Browsing/Viewing Designs Created in Earlier Versions: Designs created using earlier versions of Capture can now be opened and viewed without requiring the design to be uprev’ed. Such designs only need to be uprev’ed when the design is actually saved.
  • Closing All Tabs: Canvas tabs can now all be closed, or all but this tab closed with an RMB selection. Right-click on the tab and choose the appropriate option (Close, Close All Tabs, or Close All Tabs But This.
  • Custom Design Rule Check (DRC): Though Tcl scripting, user-defined schematic and circuit checks can be created and added to the Capture DRC routines. Several R&D examples include checks for hanging wires, device pin mismatches, overlapping wires, reference prefix mismatches, port-pin mismatches, and shorted discrete parts.
  • Project Save As Enhancements: While saving a project in 16.6, a project name that is different from the design name can be specified to mimic the manual process of copying/moving a product from one hard-drive location to another. Options include the ability to copy/move all referenced files, ensuring that all links are updated while saving.
  • RefDes Support Alignment: Capture and CIS now handle references and designators in the same manner, eliminating the need for manual Reference Designator corrections in the CIS database and BOMs. CIS now supports all reference designator formats including as U2N, C1_R, C12-1, R7-TOP, MP_2V5_REF, and TP3V3_0. Also, the reference designator for multi-packages is consistent (e.g. MP_2V5_REF will be MP_2V5_REF not MP_2V5_REFA).
  • Linking External Design Parts: Referenced parts of the external design can now be linked at the group or subgroup level.
  • CIS Performance Increase: The overall performance for CIS operations, especially when dealing with very large databases or queries, has been significantly improved.
  • Tcl Customization for CIS Explorer: CIS Explorer can be custom-configured with user-definable actions and capabilities. (For example, customized part placement checks can disable placement of an EOL part or provide a warning if part procurement has a long lead time). Query result rows can also be customized.  (For example, rows can be highlighted blue for recommended parts or red for parts not recommended or allowed.)
  • CIS Multi-Value Support: Any CIS field can now be set as multi-valued for component instances with numerous information or content sources (e.g. lists for multiple datasheets/application notes or multiple PSpice models for a component).
 
OrCAD Capture - 16.5
  • Graphical Operation Locking (GOp): The GOp locking feature in Capture now allows you to lock the different parts of a schematic design. Lock objects on a page, folder, or even the complete design. This feature prevents inadvertently moving or deleting parts of a design that are locked. Designs requiring alteration will need to be unlocked before any changes are made.
  • Placement Report: Generate a report of the X and Y locations of the placement of the parts on a schematic. This report, generated as a .CSV file, provides details of the parts including; Reference Designator, Part Name, Schematic Name, Sheet Number, File System Location of the Part Library, and X and Y co-ordinate location.
  • Find Results Report: After executing the Find command on a design, generate a report for the results from the command. By running the Find command to search for different types of objects in a design, the search results display in different tabs of the Find window, allowing you to export the data from each tab.
  • Net Groups: OrCAD Capture introduces the concept of the NetGroup that allows you to create groups of nets. A NetGroup can include a group of scalar nets, vector nets, or a combination of both. Capture allows you to create Named NetGroups that can be used across a design or exported to other designs. Alternatively, for one-time use, you can create an Unnamed/Adhoc NetGroup. The new NetGroup Connector can be used to intelligently merge and tap out signals. It can also be used to generate net names for connected signals.
  • CIS.INI Settings: While the Capture INI settings are always dynamic, the CIS settings are more or less static and usually do not change after the initial CIS database related setup. You may often need to clear out and reinitialize your Capture INI settings, but may still want to retain the CIS settings. To allow this, OrCAD 16.5 now retains the CIS INI settings in a separate back-up file. This file retains the CIS INI settings that Capture will retrieve when it re-initializes the Capture INI settings.
  • Partial Design Simulation: The 16.5 release comes with the productivity enhancing feature of partial design simulation. You can now identify individual components of any design, and, using the partial design simulation feature, simulate only selected portions. Using this feature, you can simulate different circuits in the design with different simulation profiles. You can also netlist only a particular portion of the design. In addition, you can compare and merge portions of a design quickly.
 
OrCAD Capture - 16.3
  • Auto Wiring: In complex designs containing a large number of parts, the task of wiring the parts together is often a time consuming and tedious task. Wiring multiple pins to a bus can also be a tedious and repetitive task. Capture now includes an Auto-Wiring feature that allows you to wire two or more pins or wires on your schematic page. To wire multiple points on your page, you simply need to select all the points and choose the available Auto Wiring options (Auto-Wire Two Points or Auto-Wire Multiple Points). Besides wiring multiple points on your page, you can also wire points to a bus using the Auto-Connect to Bus option.
  • Associate Project Type: When you create a new project in Capture, you select the project type. After working on the project you may need to change the project type. For example, you may need to change the project type from Schematic to Analog or Mixed A/D type. Capture now includes the option to change the project type of any existing Capture project.
  • Design Navigation Improvements: Capture 16.3 now allows you to create Intersheet references on flat designs, simple as well as complex hierarchical designs. Design navigation in Capture now also includes signal navigation feature to navigate the connected signals on a design. This feature allows you to select a signal that you want to trace Capture then browses for all the connected signals on the design. Finally, you can select and highlight the signals from the browse list.
  • Wire Styling Options: You can now change the look and feel of a wire or a net on a schematic page by changing the color, line style or line width.
  • Color Part: Capture now allows you to alter the look and feel of the block to change the color of a specific block in your design. You can even add a picture to the block that acts as a visual representation of the implementation below the block.
  • Embedded Images: Now you can embed a large number of image types into a schematic page. The image types now supported by Capture include BMP, JPEG, GIF, PNG and TIFF.
  • OLE Object Support: OLE Object support in Capture allows you to embed or link an object on your schematic page. The object types that you are allowed to embed or link are defined by the applications and files available on your computer. This feature allows you to annotate your schematic pages with any external data (information) that you need to enhance the usability and readability of your design.
  • Bezier Curves & Elliptical Arcs: Capture now allows you to place elliptical arcs and multi-point bezier curves on your schematic pages.
  • PCB Editor 3D Footprint Viewer: The PCB Editor 3D Footprint viewer provides a three dimensional view of the footprint symbol of a selected part on the schematic or the part editor. Along with the footprint symbol, the viewer also displays pin numbers and pin names. On the viewer, you can view a footprint from different perspectives: top, bottom, front, back, left, right and isometric (a 120° angle view). Besides viewing the footprint, you can also use the 3D measure tool to measure any distance across the footprint canvas and across the x, y or z axis on the canvas.
  • User Defined Pin Shapes: You can now create your own pin shapes Capture. You then use these pin shapes when you create new part or if you want to edit the pins on an existing part. The pin you create can include any shape available in Capture including elliptical arcs and bezier curves.
  • Scripting Support: The 16.3 release of Capture includes a scripting functionality that allows you to execute a Capture command through a command prompt. Capture also provides the facility to store and later replay the command.
  • Locking Objects on Board & Schematics: The Capture - Allegro flow now includes an object locking feature. This feature allows you to temporarily lock and object on your schematic or board while you are cross-probing. This will help to avoid shifting (with the potential of breaking connectivity) of a component on the schematic or board during the cross-probe operation.
  • Output Warnings Filter: During PCB netlist creation, you now have the option to ignore many electrical constraints such as; PROPAGATION_DELAY, RATSNEST_SCHEDULE, DIFFERENTIAL_PAIR, NET_SPACING_TYPE, etc.
  • Power pin Enhancements: Capture now includes a new Assign Power Pins command that allows you define invisible power pins as NC pins. This ensures that you then only need to route the power pins that are not set as NC pins.
  • Electrical Rules: The DRC check in Capture is now separated out between physical rules and electrical rules. So you can now choose to run design checks from the available physical and / or electrical rules.
  • Check & Save: The new Check & Save option (available through the project manager File menu) allows you to run a DRC on the currently checked electrical rules in the DRC dialog. Since the DRC rules are defined by project, you need to define the electrical rules for a project and run the DRC check once on the current project. Subsequently, you can use this shortcut to execute the selected electrical DRC checks on the design.
 
OrCAD Capture - 16.2
  • Usability enhancements
  • Enhanced OrCAD Capture and PCB Editor integration
  • Improved FPGA design-in functionality
  • New annotation type option
  • DRC enhancements
  • Netlist enhancements
  • L2A integration in OrCAD Capture
  • User interface updates
  • CIS RDBMS support
  • CIS configuration file in XML format
  • New ActiveParts Portal in ICA
 
OrCAD Capture - 16.0
  • Place and move drawing objects on fine grid independent of connectivity objects
  • Enhancements to archiving mechanism for PSpice model libraries
  • Cadence Help
  • Support for mechanical parts and assemblies in standard CIS BOM
 
OrCAD Capture - 15.7
  • Controlled annotation of parts
  • PSpice ground zero symbol
  • Mouse wheel support
  • New option to set the drag behavior
  • New unit values in the signal flow properties UI
  • Customize netlist formatter
  • Descend hierarchy using the mouse button double-click
  • Saving queries
  • Version 11.0 of Crystal Reports
 
OrCAD Capture - 10.x
  • 10.5 - Split part symbol generation enhancement
  • 10.5 - Archiving enhancement
  • 10.5 - Differential pairs between flat nets
  • 10.5 - New part creation from spreadsheet
  • 10.5 - Assigning signal flow properties to a bus
  • 10.5 - Setting preferences for linking a placed part to a database part
  • 10.5 - Viewing design variants information
  • 10.3 - Split part symbol generation
  • 10.3 - Signal property flow to PCB Editor
  • 10.3 - Page navigation
  • 10.3 - Replace cache with preserve reference designator
  • 10.3 - Import the latest Xilinx and Altera formats
  • 10.0 - Design-level property management
  • 10.0 - Unlimited undo/redo
  • 10.0 - Label states for what-if scenarios
  • 10.0 - Enhanced support for simulation profiles
  • 10.0 - New directory structure for analog projects
  • 10.0 - Annotation improvements
  • 10.0 - Soft save
  • 10.0 - Automatic backup of designs
  • 10.0 - Dynamic port/pin updates on hierarchical blocks
  • 10.0 - File locking for team design
  • 10.0 - Ability to run multiple versions of OrCAD Capture
  • 10.0 - Printing and plotting enhancements
  • 10.0 - Support for design reuse in OrCAD Layout
  • 10.0 - Significant improvements in OrCAD Capture-Allegro PCB flow
  • 10.0 - Push occurrence properties into instance utility
  • 10.0 - Support for Xilinx Design Manager version 4.1 and 4.2 output files
  • 10.0 - Improved EDIF 2.0.0 import/export functionality

OrCAD PCB Designer - 17.2-2016

Please view the matrix to see which level the features appear in

      - Stack up by zone: The new feature improves MCAD-ECAD co-design and provides faster, easier definition of stack-ups for rigid-flex rigid designs.

      - Inter design layer checks: The new inter layer functionality provides ability to check geometries between two different class/ subclasses for flex and rigid flex designs.

      - Arc routing - A new prototype feature to provide more efficient method to add routing during Add Connect by following an existing connect line or a route keep-in.

  • Cross section editor- Redesigned Cross Section Editor based on the spreadsheet technology found in Constraint Manager to provide one stop shop for features requiring cross section for their setup.
  • New padstack editor – Introducing modern user interface for convenient padstack creation with addition of new geometries and support for counter-bore/ counter-sink definitions and several new drill features.  (Watch Demo Video)
  • Shape Edit Application Mode –Introducing new functionality that is a fine tuning editing environment to increase efficiency with shape boundary editing and simplifying actions such as sliding a shape edge or adding a notch etc.
  • Color and Visibility enhancements – The Color Dialog box has been enhanced for better efficiency and ease of use for designers and the Visibility pane now provides access and control over layers other than the conductor layers.
  • 64 Bit Support – Now available support for 64 bit OS with increase in memory size from 4GB to 18 Quintillion and support for Database sizes upto 3GB.
  • More gains in performance for CPU intensive applications.
  • ​Display segment over voids – A new command Segment Over Voids detects cline segments crossing adjacent plane layer voids. (Watch Demo Video)
  • Spread Line between Voids – New command to provide semi-automatic solution to spread channel based clines with respect to adjacent plane layer voids.
  • Via2Via Line Fattening- Users can increase line width between vias based on their definition of edge to edge clearance by using the “Line fattening” utility. (Watch Demo Video)
  • Contour routing- Now available in both single and mutli-routing modes, contour hugging locks the current route to either the route keepin or adjacent cline.
  • Group routing – User can now perform group routing by window selecting around a group of objects(Clines, Vias, Pins, Rats) and be able to change the control trace from its initial location to user defined and go into single trace mode to complete routes.
  • Gloss Commands – Richer set of gloss commands like Eliminate Vias, Convert corners to ARC, Fillet and Taper traces and many more now available in OrCAD PCB Designer.
  • Differential Pair Routing and DRC – Users can now define physical and electrical rules for Differential pairs complemented by routing support.
  • ​Layer Set DRC and Routing – The new layer set functionality insures layer constrained nets are routed to wiring requirements by ‘locking routes’ to within the appropriate layer set(s) for the net based objects. (Watch Demo Video)
 
OrCAD PCB Designer - 16.6 QIR#6
  • Intelligently Exchange Stackup Information with IPC-2581: Automatically import and export stackup information from Allegro with the open IPC-2581 standard. This reduces manual entry errors and enables better collaboration and planning with manufacturers early in the design stage.
  • IDX ECAD-MCAD Enhancements: A number of enhancements have been added to incremental data exchange (IDX) format for ECAD-MCAD collaboration
    • Bend Area Support: Flex circuit bend areas can be defined and/or imported from MCAD. Keepouts will automatically be generated and the bend area visually displayed on the PCB Editor canvas.
    • Multiple Heights for Components: Extruded components can contain multiple height areas using IDX.
    • Component Height DRC Updates: Component Height DRC can now account for global offset used to account for mask thickness.
    • User Defined Layers Exchange: Import/Export of user defined layers is now supported in IDX.
    • Copper Exchange: External layer etch can now be passed to the MCAD environment from PCB Editor. Allows for collaboration on Faraday cages and thermal analysis.
    • ECAD MCAD Data Compare: Verify MCAD and ECAD data are in synch before committing to manufacture. New compare tool will display differences visually in PCB Editor.
  • File Locking Improvements: Additional capabilities have been added to specify file locking duration and what protocol to use to check lock time against.
  • New Drafting Capabilities: Extend segments and trim segments drafting commands have been added
  • Split Views: View multiple areas of the board at once with new split views feature. Great for helping with bus breakout routing and unraveling at each end of the interface.
  • Find By Query (Unsupported Prototype): New query building engine to provide finer grained search and filter capabilities with AND, OR, and NOR logical operators
  • Windows 8.1 Support: OrCAD is officially supported on Windows 8.1.
 
OrCAD PCB Designer - 16.6 QIR#5(QIR #5 Factsheet)
  • Move Components with "Slide Etch" Option: New option designed to reroute etch attached to components being moved using conventional angles (45, 90).
  • Dynamic Rat Suppression: When ‘Add Connect’ command is invoked, all rats except the active net are temporarily suppressed
  • New Drafting Commands: Added the relative move & copy command to move and copy elements about a user specified axis
  • Text Block Name Field: Select Text block by functional name (Assembly, Silkscreen, etc)
  • Snap Pick Enhancement: Can now snap pick to pad edge, pad edge midpoint, and pad edge vertex
 
OrCAD PCB Designer - 16.6 QIR#4
  • STEP Support Enhancements: STEP support has been enhanced with the following new and improved capabilities:
    • Zoom capability was added to the mapping environment to aid in faster and more accurate STEP model mapping
    • Added fine-grain keyboard arrow key control to help with model alignment
    • Added the ability to map a course and detailed 3D model to a footprint
  • Voids in Keepouts: OrCAD PCB Editor now supports voids in route keepout, placement keepout, via keepout, and test probe keepout
 
OrCAD PCB Designer - 16.6 QIR#3
  • STEP Update: Improved performance, fixed issues with export and import from MCAD tools
  • Allegro Drafting Prototypes (Early Adopter Features):
    • Delete by line
    • Delete by rectangle
    • Offset copy
    • Offset move
    • Add perpendicular line
  • Pastemask DRC Update: Shapes drawn on the package geometry, top and bottom subclasses are now factored into the DRC check
  • Database Diary: Maintain a running log of comments with the design file (Available in OrCAD PCB Designer Professional ONLY)
 
OrCAD PCB Designer - 16.6 QIR#2
  • STEP 3D and Model Support: STEP support 3D visualization, mapping, import and export (Early Adopter)
 
OrCAD PCB Designer - 16.6
  • New “Slide”: A new “slide” command utilizes a move-intersect algorithm that delivers smoother, more predictable, and localized edits
  • IPC-2581 Support: PCB Editor now supports the export of design data for manufacturing using the open industry-standard IPC-2581 format
  • Productivity Enhancements: Additional enhancements for ease-of-use and productivity include:
    • Fix Cline segments
    • Create parameterized rectangular shapes with rounded or chamfered corners
    • Overlay net names within clines, pins, shapes, and flow lines
    • DRC by window
    • Align components top, bottom, or center using DFA rules
    • Spread or compact aligned components using + or – buttons
    • Highlight all nets associated with a component
    • Identify film records associated with artwork, IPC-2581, PDF out, and visibility using just one form
    • Use pastemask-to-pastemask DRC to check against the package geometry
    • Select by “lasso” or “path”
  • New Design Defaults: New designs can be automatically seeded with default template design, just default units and accuracy, or a template design containing anything including units and accuracy, parameters (including colors), constraints, and physical data
  • Database Diary: Maintain engineering and design notes as part of the database
  • Significant Display Performance Improvements: OpenGL has been optimized to improve display performance along with several new enhancements, including new net highlight method, embedded net names, and new display option that overlays net names on clines, pins, and shapes
  • Moving Elements Enhancements: Permits select elements to be moved outside present class/subclass structure (limited to lines, line segments, text, and rectangles)
  • Artwork Control Form and Drill Updates: Several new updates include:
    • RS274X supports output of shape with voids overlapping other shapes
    • Film name lengths increased from 17 to 46 characters
    • Artwork suppresses Null pads when unused pad suppression is enabled
    • photoplot.log generates a warning if un-defined line width is set to 0
    • Initial artwork parameters default to same unit type as board
    • Creating new drill data reports the number of holes

Thieving Updates: New thieving enhancements include add thieving to “all layers” in a single execution, add thieving by a “rectangle selection”, and add thieving to all soldermask layers

 
OrCAD PCB Designer - 16.5
  • New OrCAD Suites:
    • OrCAD PCB Designer Standard (formerly OrCAD PCB Basics) without limitations of numbers of pins and net layers
    • OrCAD PCB Designer Professional (formerly OrCAD PCB Designer) with a larger number of high-speed features, constraint management capabilities, and included signal integrity analysis

 

  • General Updates (All Tiers)
    • GUI updates
      • Access the status bar: Classes, sub-classes, and the Super Filter Modes applications and selections are available by the bar status of the tool
      • Textures of the color: Fixtures are differentiated with filling and customizable, each color panel coloring can be completed by a texture
      • Zoom-in window pick: Refreshes the display on a point or precise coordinates
      • Differentiation between insulation and short-circuit DRCs: Net shorting the DRC are short-circuits and recognized as such in the error-count DRCs
    • New commands
      • Minimum metal-to-metal DFF checks: Ensures that the distance between objects and copper is inspected, particularly when certain spacing rules are disabled
      • Duplicate drill hole: This audit checks for overlapping holes at the same coordinates
      • Table of cross-section: This new command allows creation of a cross-section image of the PCB with all types of vias used on design
      • Placement: The import file placement now includes an option to import components to contact with the face and the angle indicated in the file place_txt.txt
      • Viewing via label: As soon as a blind via, buried, or μvia is used, its label can be displayed

 

  • New Placement Mode: Dedicated environment for tailored placement tasks:
    • Single click to move a component.
    • Accessible by simply passing through the object
    • Alignment of components
    • Placement replication (including etch)

 

  • Constraints and High-Speed Design (PCB Professional Only)
    • Differential Pair Support: Differential pairs can be routed according constraints with DRCS recognized by the constraint manager (primary gap, length uncoupled, coupled tolerance, gap and neck width)
    • Rules by zones (Regions): Stress areas are present in the Structure Constraint Manager, with rules routing and physical spacing by region, region class, region class-class, same net, differential pair gap, width, and layer
    • Min/max etch-length constraints: Total etch-length control is possible on the net in the Constraint Manager with a minimum and maximum distance
    • Delay tuning: The length adjustment (Delay Tune) is available using forms of elongation type accordion, trombone, and teeth saw
    • Automated test prep: Automatically generate test points for test fixtures in PCB

 

  • Other Updates
    • 3D display: Added option for dynamic update of PCB layers
    • File lock: When sharing files, it is possible to have multiple open instances of the same file. The *.lck file now protects the edited file from being overwritten
    • Pad behavior: When the Enhanced Pad Entry option is selected when routing or sliding, the pads based on a form of shape are now recognized
    • Delete via structure: The structure of vias created with the fanout command can now be deleted
    • Color: The Color View window has a Save option, Flip Preserve State
 
OrCAD PCB Designer - 16.3
  • 3D Viewer: The new 3D environment supports several filtering options; camera views; graphic display options such as solid, transparency, and wireframe; and mouse-driven controls for pan, zoom, and spinning the display. 3D viewing is also supported in pre-selection mode, making it possible to display HDI via structures or isolated sections of the board
  • Flip Design: You can now view the layout of the PCB from the bottom side. In addition to viewing, design edits such as moving silkscreen text can be performed while in this mode
  • Enhanced Pad Entry: Interactive etch editing has been enhanced to improve the transitioning of clines exiting and entering a padstack. The enhanced pad entry works on circle, rectangle, and oblong pads by exiting perpendicular to a pad edge, or exiting out a radius at an angle that does not produce an acute angle
  • Pastemask Clearance DRC: Pastemask-to-pastemask clearance check helps ensure there is sufficient solder paste gap between objects, preventing paste from shorting to other objects
  • Multi-Threading Support for DRC: Multi-threading support is integrated with the DRC system and supported on dual and quad configurations
  • Productivity Enhancements: Productivity enhancements include an enhanced windowing operation that permits a polygon selection window, customizable datatips through a user-configuration interface, and the measurement of the separation between any two objects, regardless of the layer, by the Show Measure menu
  • Jumper Support: New methodology supporting jumpers in the Etch Edit environment
  • Drawing Origin Display: A new interactive command allows you to easily locate and display the drawing origin in the canvas
  • Color Dialog Update: Subclass forms within the Color dialog can be increased in vertical length by selecting the “Hide Palette” button located at the bottom of the form
  • Display Pin Number Update: Pin number display is now aligned with top- and bottom-layer visibility
  • Negative Plane Sliver DRC: New DRC to detect small, undesirable web of copper between two objects on a positive or negative layer that can result from the placement of two pin or via objects in close proximity to each other
  • Route Keepout—Pin Detection: New DRC check to detect the presence of a pin within the boundary of a Route Keepout shape
  • Route Keepout—Allow Shapes Options: Define Route Keepout area to permit shapes within that defined area
  • Dynamic Shapes Performance Improvements: ~25% performance improvements in shapes performance for more complex designs
 
OrCAD PCB Designer - 16.2
  • Etch Edit Applications
  • Manufacturing Applications
  • Padstack Enhancements
  • Design-Level DRCs
  • Productivity Enhancements
  • Miscellaneous Productivity Enhancements
  • Color and Graphics
  • Miscellaneous Manufacturing Applications and Interfaces
  • Database Enhancements
 
OrCAD PCB Designer - 16.0
  • Usability/New Use Model
  • PCB Editor User Interface
  • Color and Visibility Enhancements
  • Physical and Spacing Constraint System
  • New PCB Editor Application Modes
  • Miscellaneous PCB Editor Enhancements
  • OrCAD Layout Translator Updates
 
OrCAD PCB Designer - 15.7
  • OrCAD Layout to OrCAD PCB Editor Support
  • New Class of Soldermask DRCs
  • Soldermask Clearance
  • New Room_Type Properties for DRC Flexibility
  • Copy Command
  • Auto-Save
  • NC Legend Enhancements
 
OrCAD PCB Designer - 10.x
  • 10.5 - Thieving
  • 10.5 - NC Drill
  • 10.5 - Interactive Etch Editing Improvements
  • 10.5 - Usability Enhancements
  • 10.5 - Interfaces Enhancements
  • 10.5 - Library Editor Enhancements
  • 10.5 - Miscellaneous Enhancements
  • 10.3 - Introduction of OrCAD PCB Editor Based on Allegro PCB Editor Technology

OrCAD PSpice Designer - 17.2-2016

Please view the matrix to see which level the features appear in
 
Virtual Prototyping:  New functionality for automating the code generation for multilevel abstraction models written in C/C++, and SystemC, VerilogA-ADMS, and a set of behavioral analog  devices and controlled sources. (Watch Demo Video)

64 Bit Simulation Engine and Result Analysis – Leverage full potential of compute platform to perform simulation and waveform analysis on extremely large designs.  

  • New functions for Behavioral models – a set of Delay() functions to introduce delay in behavioral models or controlled sources.
  •  New Models – Models for TinySwitch-III family devices and new Optocoupler devices have been added
  • Support for TCL 8.6  - In 17.2 release Capture and PSpice support TCL 8.6.
 
OrCAD PSpice Designer - 16.6 QIR#7(QiR #7 Factsheet)
  • PSpice Learning Resources Update: Users can use the new Digital Electronics and Data Convertors chapters with working examples that have been added to the Basic Electronics book in Learning PSpice.
  • Speed Upgrades: Users can take advantage of the 5 levels of speed upgrades with the default set at a level 3, (speed level should be set at 0 for compatibility with previous releases). The speed levels will allow for faster switching of devices and show substantial improvement from the previous release.
  • Enhanced Multicore Support: Removed multi-core usage limit (previously maxed out at 4 cores).
  • Convergence Improvements: With QIR7 improvements, users are recommended to use lower values of ITL4 to achieve convergence and performance compared to previous releases requiring high ITL4 values using Switches circuits to achieve convergence. This will help to eliminate performance and mathematic errors.
  • Hysteresis Core Loss Calculator: Users can now use this app that measures Steady State loss of energy in a magnetic core for power supplies.
  • New Simulation Reporting Capabilities: Users are now able to generate an HTML report for Analog Transient simulation where average, RMS, and Peak values of Current, Voltage, and Power can be reported. This is user customizable and there is a TCL source available in the installation hierarchy.
  • Enhanced PSpice Model Search Utility: Now PSpice Advance Analysis libraries, such as, aa_igbt.olb, and so on are added to the PSpice Part Search database so you are able to search and then place in your designs. The symbol viewer within the Searcher has also been updated.
  • Object Distribution Feature: Enhanced to force equal spaced distribution by default.
 
OrCAD PSpice Designer - 16.6 QIR#6
  • Windows 8.1 Support: OrCAD is officially supported on Windows 8.1
 
OrCAD PSpice Designer - 16.6 QIR#5(QIR #5 Factsheet)
  • Temperature Sweep for Monte Carlo: With this new PSpice app, multiple runs of Monte Carlo can be run sweeping at different temperatures.
  • New PSpice Modeling Applications: PSpice modeling applications for Switch, Transient Voltage Suppressors (TVS), Voltage Controlled Oscillator (VCO), Independent Sources, and PieceWise Linear (PWL) Sources have been added to Capture
  • Random Function for PSpice Simulation: A new, supported Random function has be added to the PSpice Engine eliminating the previous work-around that required a PieceWise Linear (PWL) source set to auto-repeat.
 
OrCAD PSpice Designer - 16.6 QIR#4
  • Frequency Response Analysis: New method to calculate open loop gain for switching circuits from transient analysis using Middlebrook's Method (blog article)
  • Learning PSpice Update: Added a new Power Electronics module. Complete theory and design with examples included. Accessible through Help>Learning PSpice
  • Comments as OrCAD PSpice Directives: All comments in the Capture canvas starting with @PSpice are net-listed into the .cir file. Used to quickly define commands not available through standard PSpice setup GUI
  • Option to Ignore DML Error: New option in the IBIS2Spice command to DML checks and attempt at translating to Spice.
  • New Convergence Options: The following convergence options are now available in .OPTIONS
    • PREORDERMODE
    • MINSIMPTS
    • RMIN
    • BPPseudoTran
    • TRANCONV1
  • Global Parasitics Support Convergence Option: Ability to set minimum parasitics for the following devices
    • BJT
    • JFET
    • MOS
  • Expression Support: Now available for the .TRAN, .OPTIONS, and .FOUR commands
  • .dat File Post Processing: TCL function support in circuit file allows automated post-processing of any PSpice output file
  • OrCAD Capture Simulation Parameters: New Probe statement supports P() function to capture parameter values in .DAT file
 
OrCAD PSpice Designer - 16.6 QIR#3
  • Option to Apply Parasitics Globally: On analysis of a large number of OrCAD PSpice designs, it was found that a number of issues were caused by ideal devices (without parasitics). For example, using an ideal diode with parasitics can lead to convergence and performance issues as the simulator quickly moves to very small timesteps and often goes over minimum timestep thresholds. New options are available to set a minimum parasitics value level for diodes and Bipolar Junction Transistors (BJT) globally.
  • "10p files for Convergence Failure" Option: This option allows the operating point values even if a convergence failure has occurred, thereby avoiding situations where the user is left with previous bias point values on convergence failure
  • CSHUNT On/Off Option: In a number of cases, the nodes values do not stabilize because one or more feedback path has no delay in path. Successive iterations within OrCAD PSpice solver result in node oscillations and convergence errors. The OrCAD PSpice 16.6 QIR 3 provides a CSHUNT option that adds capacitors of specified value to the nodes. While a default value of 1.0E-12 is recommended, it can be changed on a case-by-case basis
  • Enable Continuation Methods: This series of transient convergence methods allows OrCAD PSpice simulator to override default solution search schemes and apply other heuristic algorithms, and is applied when all other options have failed. An example of such an algorithm is to reject the last successful time point and start working out the simulation solutions from the time point previous to the last successful time point. Additional heuristic algorithms will be added under this option in subsequent releases
  • Learning OrCAD PSpice Technology and Adding Your Own Content: A new chapter is available in the Learning OrCAD PSpice module. This chapter explains the steps required to add your own content, lessons, or app notes to OrCAD PSpice environment
  • Subcircuit Definition: Subcircuit definitions in OrCAD PSpice environment can now support any character length
  • Fourier Output: Fourier output now supports NUMDGT
 
OrCAD PSpice Designer - 16.6 QIR#2
  • OrCAD PSpice Modeling App: FREE app to enable quick and accurate creation of OrCAD PSpice parts directly on the OrCAD Capture schematic using a wizard-style interface. The first version of the app includes the following model generators. This app can be downloaded at the OrCAD Capture Marketplace
    • Sources
    • RF Inductor
    • Zener Diodes

​

  • Advanced Simulation Options: Options have been added to the Advanced Analog Options dialog box for improved convergence:
    • Shunt Capacitance (CSHUNT)
    • Diode Ohmic Resistance (DIODERS)
    • Diode Junction Capacitance (DIODECJO)
    • Alternate Path Search (TRANCONV)
    • Debugging Convergence Failure (CONVAID)
    • Bipolar Junction Transistor (BJT) Capacitance (BJTCJ)
 
OrCAD PSpice Designer - 16.6
  • Advanced Control Options: Numerous advanced convergence and simulation control options/parameters have been added or exposed, giving users greater control over simulation and convergence. These options include: bias-point convergence, voltage limiting, worst-case deviations, max-time step control, pseudo transient, and relative tolerance
  • Probe .dat Upgrade to 64-bit Precision: OrCAD PSpice technology now generates 64-bit data precision in the .dat file output. This ensures higher precision compared to the 32-bit .dat file data from previous releases. (As an example, in previous releases, when a very small amplitude voltage is superimposed on a large voltage, the resulting voltage lost its resolution in a 32-bit .dat file.)
  • UNDO Support for Captured Netlists: Netlisting to OrCAD PSpice environment now preserves UNDO, making it easier to make iterations and modify parameters, components, and connectivity
  • Enhanced IBIS Support: The IBIS to OrCAD PSpice model now supports V-T curves for all IBIS models up to version 5.0
  • Multi-core Engine Support: Enhancements to multi-core support and I/O read-write provide significant performance improvements. Focused performance enhancements, especially for large designs or designs with complex model instances (MOSFETS, BJT), also boost performance
  • Encryption Enhancements: Upgraded model encryption now includes 256-bit (AES) encryption support
  • Tcl-based Customization: Advanced Analysis, simulation, and .dat file access can be accessed and extended with user-definable actions and capabilities. This enables an environment that can be enhanced to specific flows and needs, and allows users to leverage enhanced features and design capabilities
 
OrCAD EE (PSpice) Designer - 16.5
  • New Models
    • MOSFET Drivers
    • Alkaline Battery
    • Optocouplers
    • Voltage Mode Control PWM Controller Models
    • Offline Switches
    • Power Inductors
    • Solid State Relays
    • Charge Pump-Based DC/DC Regulator
    • Integration of Operational Amplifier Models from vendor

 

  • Partial Design Simulation: This productivity-enhancing feature allows you to identify individual components of any design, and, using the partial design simulation feature, simulate only selected portions. You can simulate different circuits in the design with different simulation profiles, as well as netlist only a particular portion of the design. In addition, you can compare and merge portions of a design quickly.
 
OrCAD EE (PSpice) Designer - 16.3
  • OrCAD PSpice A/D Waveform Makeover and New Usability Improvements: Enhanced cursor support, and new simulation models. OrCAD PSpice Advanced Analysis contains all the productivity and usability improvements highlighted in OrCAD PSpice A/D environment
  • Easy To Use Pop-Up Menu for Traces: The context-sensitive menu for traces is now more usable with all the trace related options grouped together. When users select a trace and right-click, they are presented with the options in context of the trace
  • Easier Access to Trace Properties: Users can now choose the Trace Property option in the Trace pop-up menu to open the Trace Properties dialog box. This dialog box gives a range of choices to change color, pattern, width, and symbol for a selected trace, making it easier to identify individual traces. This dialog box also allows users to easily hide all traces or show all traces
  • Background and Foreground Color Control: Users can now specify different colors for the background of the Probe window, as well as grids and axis lines in the foreground
  • Customization of Trace Color Auto-Rotation: OrCAD PSpice A/D 16.3 users can choose to change the default trace colors from an extended list of 145 supported colors
  • Cursor Width and Color: The Cursor Settings tab of the Probe Settings dialog box allows users to specify the vertical and horizontal width and color for two cursors. The number of cursor digits can also be specified
  • Placement of Cursors Across Multiple Traces and Plots: OrCAD PSpice A/D 16.3 users can add cursors across multiple traces and plots. The cursor window displays values for the different traces
  • Export and Copy of Cursor Data: OrCAD PSpice A/D 16.3 users can export the cursor information to a comma separated value (.csv) file that can then be opened in a spreadsheet application, such as Microsoft Excel. Users can also copy selected values from the cursor window and paste the information from the clipboard to any text editor
  • Dockable Cursor Window: In OrCAD PSpice A/D 16.3 environment, the Cursor window is dockable and can be placed anywhere the user finds convenient
  • Export of Comma Separated (CSV) Files: Users can now easily export trace information as .csv files by choosing the File Export Comma Separated option in the OrCAD PSpice A/D Probe window. The trace information for specified variables will be exported to a location and file specified by the user and can be read using a spreadsheet application, such as Microsoft Excel
  • Faster .dat File Import and Export: In previous releases, the performance of large .dat files 2GB or more in size was improved. In the 16.3 release, the performance of opening a .dat file has been enhanced for files of all sizes
  • Highlighting In Circuit And .out Files: In OrCAD PSpice A/D 16.3 environment, circuit and .out file syntax are presented in easy-to-read colors that highlight different groups, such as text, numbers, comments, expressions, operators, and keyword. Users can also specify their own color schemes for the files
  • New Design Templates: OrCAD PSpice A/D 16.3 environment comes with a set of design templates covering basic electronics circuits and SMPS topologies. These design templates cover the range of analog, digital, and mixed designs. Users can use the new design templates, which are a combination of design and simulation profiles, as a starting point for new designs
  • New Models in 16.3: More than 330 new models are now available for simulation in OrCAD PSpice A/D 16.3 environment under the following categories: 
    • Pulse Width Controlled (PWM) Models
    • Linear Regulators
    • Zener Voltage Regulators
    • Glass Passivated Zener Diode
 
OrCAD EE (PSpice) Designer - 16.0
  • Checkpoint restart
  • Auto-convergence
  • Run in resume mode accessible from GUI
  • Minimum step size
  • Usability enhancements
  • Improvement in performance
  • Cadence Help
  • Documentation enhancements
 
OrCAD EE (PSpice) Designer - 15.7
  • Encrypting OrCAD PSpice models
  • New Windows XP look and feel
  • Faster invocation of tool
  • New and improved documentation interface
  • New vendor libraries: IRF, Vishay Siliconix, Coilcraft
  • Better integration with OrCAD PSpice SLPS interface
  • REFDES-based filter in OrCAD PSpice Advanced Analysis
 
OrCAD EE (PSpice) Designer - 10.x
  • 10.5 - Enhanced behavioral support
  • 10.5 - Support for Philips Mextram 504 model
  • 10.5 - Model import wizard
  • 10.5 - Magnetic Parts Editor
  • 10.5 - Support for European notation
  • 10.5 - Behavioral libraries
  • 10.5 - New vendor models
  • 10.3 - Monte Carlo history support
  • 10.3 - Import waveforms
  • 10.3 - SPLS interface
  • 10.3 - Version information
  • 10.3 - Battery model
  • 10.3 - Model enhancements
  • 10.3 - Probe enhancements 
  • 10.0 - Enhancements in the support for simulation profiles
  • 10.0 - New directory structure for analog projects
  • 10.0 - Support for BSIM3 version 3.2 MOSFET model
  • 10.0 - Advanced Analysis Optimizer engine enhanced to support curve-fitting
  • 10.0 - Availability of Advanced Analysis libraries
  • 10.0 - Enhancements for handling large data files
  • 10.0 - Ignoring convergence errors in multi-sweep analysis
  • 10.0 - Controlling Advanced Analysis on individual devices
  • 10.0 - Sensitivity enhancements in Advanced Analysis
  • 10.0 - Using custom derate files in the Smoke flow
 
OrCAD EE (PSpice) Designer - 16.2
  • New supported devices in Smoke analysis
  • New MOSFET device model BSIM4 support in OrCAD PSpice environment
  • User interface updates
  • New supported devices in Smoke analysis
  • Enhanced performance for large DAT files
  • New models
  • Checkpoint restart support for digital and mixed circuits