Fastest Simulator to Achieve Verification Closure for IP and SoC Designs

Cadence Xcelium Logic Simulator provides best-in-class core engine performance for SystemVerilog, VHDL, SystemC®e, UVM, mixed-signal, low power, and X-propagation. It leverages a set of domain-specific apps, including mixed-signal, machine learning-based test compression, and functional safety, that enable design teams to achieve verification closure early for IP and SoC designs.

"Our team has used Xcelium Logic Simulation to address our verification needs, and the Xcelium Multi-Core App allows us to shorten long-running DFT pattern simulations using multiple cores. Xcelium Apps enable timely validation closure, and we plan to use them in our verification flow."


Roberto Mattiuzzo, Design Manager, Microcontrollers & Digital ICs Group, RF & Communication Division, STMicroelectronics

"We use the Xcelium Logic Simulator for our advanced AI/ML and IoT designs, helping accelerate our simulation tasks. We also utilize the Xcelium DMS App to verify our mixed-signal designs. With the Xcelium simulator, we can achieve verification closure and meet our time-to-market goals."


Edward Youssoufian, Vice President of Engineering, Alif Semiconductor

"We have extensive experience using the Xcelium Simulator, and the new Xcelium Apps are a useful extension. Our automotive chips must adhere to the ISO 26262 standard, and the Xcelium Safety App has helped us ensure compliance and identify complex bugs using state-of-the-art verification techniques."


Yi Gu, SoC Design Director, AutoChips

Industry-Leading Simulation

Broad Language Support

Support for SystemVerilog, VHDL, SystemC, e, UVM, and IEEE UPF standards

Best-in-Class Performance

Automated parallel and incremental build technologies to support the compilation of big SoC designs and best-in-class simulation engines for best regression throughput, including a multi-core engine to speed-up long-running test cases

Accelerate with Apps

Xcelium Apps such as mixed-signal, machine learning-based test compression, and functional safety for ease of mixing and matching different technologies needed throughout the design and verification cycles