All content Copyright 2022 Parallel Systems Ltd.

 

1. Left-click on .\training.dsn file entry in the Project Manager window.

2. Select Edit>Browse>DRC Markers from the top menu.
The DRC errors for the Release Root Schematic appear in a Browse DRC Markers window.

3. Place the mouse between the column headings, and drag to increase the column width.
The data in each column is now clearly visible.

(You may additional DRCs reported)

4. Left-click on the Page heading to sort the error messages by page number.

5. Left-click on the DRC Detail heading to sort the error messages by design object.

6. Double-click on an error message to navigate to the schematic containing the DRC Marker.
(Double-click in the DRC Error column.)

7. Zoom into the area containing the DRC error markers as shown in the next picture.

8. Hover the mouse over the DRC Marker to see the datatip, or double-click on an error marker, to see what the DRC Marker reason is.

Correct any DRC at this point, apart from the “Net has Multiple aliases, Possible short” warnings, which will be discussed.

 

9. Save the design.

 

10. Close the schematic page, and left-click>No at the prompt to close the open window.

 

11. In the Project Manager window, left-click on .\training.dsn and select File>Save.

 

12. Left-click on the design file again, and select PCB>Design Rules Check from the top menu.

 

13. Go to Rules Setup and Physical and un-check the Check Power Ground Short option.

 

14. Left-click>OK.
The design should be free of the error messages.

15. Use File>Save to save the project.

 

End of Lab

 

All content Copyright 2022 Parallel Systems Ltd.