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OrCAD X & Allegro X Product Matrix

A tick confirms a feature is included. Named entries identify a separately purchased option. Select any red video marker to open its original technical demonstration.
249 matching features
Feature setOrCAD
X Standard
OrCAD
X Professional
ALLEGRO
X Artist
ALLEGRO
X Designer
ALLEGRO
X Designer Plus
ALLEGRO
X Venture
Feature setOrCAD X StandardOrCAD X ProfessionalALLEGRO X ArtistALLEGRO X DesignerALLEGRO X Designer PlusALLEGRO X Venture
Floating Networked LicenseView technical demo✓✓✓✓✓✓
12 Months Maintenance Support Included In Purchase PriceView technical demo✓✓✓✓✓✓
SCHEMATIC ENTRY + DATA MANAGEMENT
Flexible Window layoutView technical demo✓✓✓✓✓✓
Graphical, flat and hierarchical page editor and Picture block hierarchyView technical demo✓✓✓✓✓✓
OrCAD PSpice AD Basic - Restricted Capacity - see PSpice Matrix belowView technical demo✓✓✓✓✓✓
Net Groups - Complex bus definitionView technical demo✓✓✓✓✓✓
AutoWireView technical demo✓✓✓✓✓✓
44,000 Schematic symbolsView technical demo✓✓✓✓✓✓
Coloured Components / netsView technical demo✓✓✓✓✓✓
Tcl TK scripting supportView technical demo✓✓✓✓✓✓
Online design rule check including custom DRC capability and Waive DRCView technical demo✓✓✓✓✓✓
Forward and back-annotation of properties / pin-and-gate swapsView technical demo✓✓✓✓✓✓
Schematic Part and Library editorView technical demo✓✓✓✓✓✓
Cross-probing and cross-placingView technical demo✓✓✓✓✓✓
FPGA design-in / pin import & exportView technical demo✓✓✓✓✓✓
Multiple PCB netlist interfaces - New Design Sync for Cadence FlowView technical demo✓✓✓✓✓✓
UltraLibrarian, Samacsys and SnapMagic (Symbol, Footprint 3d Step Model)View technical demo✓✓✓✓✓✓
Property editor for pins, components, netsView technical demo✓✓✓✓✓✓
OrCAD SigXplorer SI AnalysisView technical demo✓✓✓✓✓✓
Intelligent PDF creationView technical demo✓✓✓✓✓✓
Advanced AnnotationView technical demo✓✓✓✓✓✓
Design Compare (detail and Graphical)View technical demo✓✓✓✓✓✓
Default Demo designsView technical demo✓✓✓✓✓✓
Extended PreferencesView technical demo✓✓✓✓✓✓
Export ISCF (Intel Schematic Connectivity Format)View technical demo✓✓✓✓✓✓
Export / Import XMLView technical demo✓✓✓✓✓✓
Altium Importer Schematic (PCB also available)View technical demo✓✓✓✓✓✓
Eagle Importer Schematic (PCB also available)View technical demo✓✓✓✓✓✓
Constraint ManagerView technical demo✓✓✓✓✓✓
Ability to create. manage part database schema and libraries in cloudView technical demo✓✓✓✓✓✓
Manage Virtual team and collaboration workspacesView technical demo—✓✓✓✓✓
Ability to share and work collaboratively for libraries and designView technical demo—✓✓✓✓✓
OrCAD X Cloud ServicesView technical demo10G50G50G50G50G50G
LiveBOM using Datalynq and SourcengineView technical demo—✓✓✓✓✓
Component Information SystemView technical demo✓✓✓✓✓✓
Windows ODBC compatible formatView technical demo✓✓✓✓✓✓
Interface to relational database and management systemsView technical demo✓✓✓✓✓✓
Database query for part selection and parametric propertiesView technical demo✓✓✓✓✓✓
Schematic and BOM Variants Manager (Parts not Fitted and more).View technical demo✓✓✓✓✓✓
Component Information Portal (CIP), Access to Mouser, Digikey, Future, FarnellView technical demoCIP E OptionCIP E OptionCIP E OptionCIP E OptionCIP E OptionCIP E Option
DE-HDL / System Capture——✓✓✓✓
PCB EDITOR
Markup for design reviewsView technical demo✓✓✓✓✓✓
Spacing, Same net, Netclass and Class to Class rulesView technical demo✓✓✓✓✓✓
Physical Constraint RulesView technical demo✓✓✓✓✓✓
3D DRC Rules(Component to Component, Board, Rigid-flex)View technical demo✓✓✓✓✓✓
DesignTrue DFM WizardView technical demo✓✓✓✓✓✓
Design for Test Checks (Core)View technical demo✓✓✓✓✓✓
Design for Test Checks (Advanced)View technical demo—————✓
Design For Assembly Checks (Core)View technical demo✓✓✓✓✓✓
Design For Assembly Checks (Advanced)View technical demo—————✓
Design For Fabrication Checks (Core)View technical demo✓✓✓✓✓✓
Design For Fabrication Checks (Advanced)View technical demo—————✓
Component Lead EditorView technical demo✓✓✓✓✓✓
Import File ManagerView technical demo✓✓✓✓✓✓
DFM Pad Entry / Exit RulesView technical demo✓✓✓✓✓✓
Dynamic pad suppression / Unused Pad removalView technical demo✓✓✓✓✓✓
Cross Section EditorView technical demo✓✓✓✓✓✓
Padstack Editor IPC2581 CompliantView technical demo✓✓✓✓✓✓
Application Mode (General, Etch, Placement)View technical demo✓✓✓✓✓✓
Application Mode (shape)View technical demo✓✓✓✓✓✓
Full Skill SupportView technical demo✓✓✓✓✓✓
Customisable Visibility PaneView technical demo✓✓✓✓✓✓
Dynamic Shape Pin Connection By Layer (Global/Shape/Pin/Layer)View technical demo✓✓✓✓✓✓
Dynamic Cross Hatch ShapesView technical demo✓✓✓✓✓✓
Dynamic Shapes (dynamic copper pours) Plow and HealView technical demo✓✓✓✓✓✓
Move with autoroute adjust (Slide)View technical demo✓✓✓✓✓✓
Multiple placement options, manual, quickplace, auto and roomView technical demo✓✓✓✓✓✓
Alignment x and y for components and modulesView technical demo✓✓✓✓✓✓
Dynamic rat suppressionView technical demo✓✓✓✓✓✓
Fan-out generatorsView technical demo✓✓✓✓✓✓
Interactive Routing using Working Layer (layer selection popup)View technical demo✓✓✓✓✓✓
Group route Bus Route and via patternsView technical demo✓✓✓✓✓✓
Line FatteningView technical demo✓✓✓✓✓✓
Differential Pair Static Phase Control rulesView technical demo✓✓✓✓✓✓
Differential Pairs Physical rules and routingView technical demo✓✓✓✓✓✓
Intra Differential Pairs Spacing RulesView technical demo✓✓✓✓✓✓
Via Voiding Differential PairsView technical demo✓✓✓✓✓✓
Blind Buried Single Click multiple via instantiationView technical demo✓✓✓✓✓✓
Push, Shove and Hug interactive editingView technical demo✓✓✓✓✓✓
Curve RoutingView technical demo✓✓✓✓✓✓
Snake Routing for Hex pattern ICsView technical demo✓✓✓✓✓✓
Auto Finish (Route Completion Tool)View technical demo✓✓✓✓✓✓
Scribble Sketch RoutingView technical demo✓✓✓✓✓✓
Route cleanup, optimization (Glossing)View technical demo✓✓✓✓✓✓
Embedded net namesView technical demo✓✓✓✓✓✓
Split ViewView technical demo✓✓✓✓✓✓
Through Board Transparency (OpenGL)View technical demo✓✓✓✓✓✓
Flip BoardView technical demo✓✓✓✓✓✓
Excellon NC Drill File exportView technical demo✓✓✓✓✓✓
Gerber 274X, 274D artwork OutputView technical demo✓✓✓✓✓✓
IPC2581 Import / ExportView technical demo✓✓✓✓✓✓
Import Export Mentor ODB++View technical demo✓✓✓✓✓✓
Impedance CalculatorView technical demo✓✓✓✓✓✓
Interactive / Automatic Silkscreen generationView technical demo✓✓✓✓✓✓
Import Altium PCB (schematic also available)View technical demo✓✓✓✓✓✓
Import EAGLE PCB (schematic also available)View technical demo✓✓✓✓✓✓
Import PADS & PCADView technical demo✓✓✓✓✓✓
Import IFF RF ShapesView technical demo✓✓✓✓✓✓
Import Export DXFView technical demo✓✓✓✓✓✓
Import Export IDFView technical demo✓✓✓✓✓✓
Export Intelligent PDFView technical demo✓✓✓✓✓✓
MCAD/ECAD Incremental data exchange (IDX. MCADX, AutoDESK Pluggin)View technical demo✓✓✓✓✓✓
3D/2D CrossprobingView technical demo✓✓✓✓✓✓
STEP 3D Clash DetectView technical demo✓✓✓✓✓✓
STEP 3D viewer for selected item or complete PCB.View technical demo✓✓✓✓✓✓
STEP 3D Canvas ControlsView technical demo✓✓✓✓✓✓
STEP 3D Import ExportView technical demo✓✓✓✓✓✓
STEP 3D Canvas Highlight SelectionsView technical demo✓✓✓✓✓✓
Manual Design For Test (DFT) / Test PrepView technical demo✓✓✓✓✓✓
Associative DimensioningView technical demo✓✓✓✓✓✓
Route Nets by Pick, 6- Metal Layers limit, no Pin LimitView technical demo✓✓✓✓✓✓
Route Automatic, 6- Signal Layers, no layer or Pin LimitView technical demo—✓✓✓✓✓
Net Scheduling, T-Point rules (pin to T-point), T-Point definitionView technical demo—✓✓✓✓✓
Constraint Regions, region based rules (Rigid-Flex; BGA regions)View technical demo—✓✓✓✓✓
Propagation delay rules (Relative) for nets or groupsView technical demo—✓✓✓✓✓
Propagation delay rules (Min/Max) for nets or groupsView technical demo—✓✓✓✓✓
Total Etch Length - Max/Min LengthView technical demo—✓✓✓✓✓
Extended (X)net rulesView technical demo—✓✓✓✓✓
Layer set rulesView technical demo—✓✓✓✓✓
Pin Pair rulesView technical demo—✓✓✓✓✓
Delay TuningView technical demo—✓✓✓✓✓
Dynamic Heads-up Display for critical rulesView technical demo—✓✓✓✓✓
Hug Contour routing (Flex)View technical demo—✓✓✓✓✓
Segment over void detectionView technical demo—✓✓✓✓✓
Spread lines between voidsView technical demo—✓✓✓✓✓
Shape based curve fillet support, tapered tracesView technical demo—✓✓✓✓✓
Placement replication, template based design reuseView technical demo—✓✓✓✓✓
Via array / Shielding - Shape and Trace basedView technical demo—✓✓✓✓✓
Rigid Flexi Zone ManagementView technical demo—✓✓✓✓✓
Dynamic Zone PlacementView technical demo—✓✓✓✓✓
Inter Layer Checks for Rigid FlexiView technical demo—✓✓✓✓✓
3D BendingView technical demo—✓✓✓✓✓
High Speed Analysis Impedance WorkflowView technical demo—✓✓✓✓✓
High Speed Analysis Coupling WorkflowView technical demo—✓✓✓✓✓
Placement VisionView technical demo—✓✓✓✓✓
Route VisionView technical demo—✓✓✓✓✓
Differential Pair Dynamic Phase Control rulesView technical demo—✓✓✓✓✓
Package Pin Delay (for die-2-die delay) rulesView technical demo—✓✓✓✓✓
Z-Axis delay feedbackView technical demo—✓✓✓✓✓
BackdrillingView technical demo—✓✓✓✓✓
Automatic Design For Test (DFT) / Test PrepView technical demo—✓✓✓✓✓
PanelizationView technical demo—✓✓✓✓✓
BatchplotView technical demo——✓✓✓✓
Coil DesignerView technical demo——✓✓✓✓
Custom VariablesView technical demo——✓✓✓✓
Polar GridView technical demo——✓✓✓✓
Automatic Post ProcessingView technical demo——✓✓✓✓
Z-DRCView technical demo———✓✓✓
Match / Max Via Count rulesView technical demo——✓✓✓✓
Offset RoutingView technical demo———✓✓✓
Design planning - Create hierarchical BundlesView technical demo———✓✓✓
Design planning - Create, Edit Flows, Assign Flows to LayersView technical demo———✓✓✓
Dynamic Shape based curve fillet support, tapered tracesView technical demo——✓✓✓✓
RF TracesView technical demo——✓✓✓✓
Design Link (Link Constraints from multiple boards)View technical demo———✓✓✓
Design For Assembly - Placement ControlView technical demo———✓✓✓
Electrical Constraint Set (ECSet) ReuseView technical demo———✓✓✓
Chip on BoardView technical demo———✓✓✓
Allegro Constraint CompilerView technical demo————✓✓
High Speed Return Path DRCView technical demo——✓✓✓✓
Timing Environment - Auto Delay Tune (AiDT), Auto Phase Tune (AiPT), Remove TuningView technical demo————✓✓
Tabbed RoutingView technical demo————✓✓
Electrical Constraint rule set (ECSets) / Topology ApplyView technical demo————✓✓
Electrical rules (Reflection, Timing, Crosstalk)View technical demo———✓✓✓
Advanced Constraints (formulas, relational)View technical demo————✓✓
Fibre Weave Effect Zig Zag Auto InteractiveView technical demo————✓✓
Static Phase Via Transition DRCView technical demo——✓✓✓✓
Single net Return Paths ViasView technical demo————✓✓
Differential Pair Return Path ViasView technical demo————✓✓
High Speed Via StructuresView technical demo————✓✓
High Speed Inductance Via StructuresView technical demo————✓✓
Creepage and Clearance VisionView technical demo—————✓
Return Path DRC VisionView technical demo————✓✓
Impedance DRC VisionView technical demo————✓✓
Topology Extraction WorkflowAuroraAuroraAuroraAuroraAuroraAurora
Interconnect Model Extraction WorkflowAuroraAuroraAuroraAuroraAuroraAurora
Crosstalk Workflow (Load results only)View technical demoAuroraAuroraAuroraAuroraAuroraAurora
Return Path Workflow (Load results only)View technical demoAuroraAuroraAuroraAuroraAuroraAurora
Power Inductance Workflow (Load results only)View technical demoAuroraAuroraAuroraAuroraAuroraAurora
IR Drop Analysis Workflow (Load results only)View technical demoAuroraAuroraAuroraAuroraAuroraAurora
Reflection Analysis Workflow (Load results only)View technical demoAuroraAuroraAuroraAuroraAuroraAurora
Thermal Workflow (Load results only)CelsiusCelsiusCelsiusCelsiusCelsiusCelsius
Constraint Manager: HDI rule setView technical demo——✓✓✓✓
Micro-via and associated spacing, stacking and via-in-pad rulesView technical demo——✓✓✓✓
Constraint driven HDI design flowView technical demo——✓✓✓✓
HDI micro-via stack editingView technical demo——✓✓✓✓
Creepage and Clearance RulesView technical demo—————✓
Manufacturing rule support for embedding componentsView technical demo—————✓
Embed components on inner layersView technical demo—————✓
Support for Cavities on inner layersView technical demo—————✓
Support for Vertically placed components on inner layersView technical demo—————✓
Soldermask for embedded components—————✓
Support for copy and swap embedded components—————✓
Dual Side Contact Embedded ComponentsView technical demo—————✓
Custom DRC rules using Ravel (Run capability)———✓✓✓
Custom DRC rules using Ravel (Developer)—————✓
Generic GPU Acceleration (Nvidia, AMD, Intel)—————✓
Power Delivery Generator—————✓
Design Planning - Plan Spatial Feasibility analysis & feedbackView technical demo—————✓
Design Planning - Generate Topological PlanView technical demo—————✓
Design Planning - Convert Topological plan to traces (CLINES)View technical demo—————✓
Auto Interactive Break-out (AiBT)View technical demo—————✓
Auto Connect (Breakout, Connect, Compress, Spread, Nudge, Push)—————✓
Symphony 2 user Team Design using OrCAD X Presto (cloud based)—Option————
Symphony Team Design Option, one board with multiple designers in real timeView technical demo——Symphony Team DesignSymphony Team DesignSymphony Team DesignSymphony Team Design
Parameterized RF etch elements——Analog / RF OptionAnalog / RF OptionAnalog / RF OptionAnalog / RF Option
Asymmetrical Clearances——Analog / RF OptionAnalog / RF OptionAnalog / RF OptionAnalog / RF Option
RF Etch elements editing——Analog / RF OptionAnalog / RF OptionAnalog / RF OptionAnalog / RF Option
Bi-Directional interface with Agilent ADS——Analog / RF OptionAnalog / RF OptionAnalog / RF OptionAnalog / RF Option
ADS schematics Import Agilent into DE-HDL——Analog / RF OptionAnalog / RF OptionAnalog / RF OptionAnalog / RF Option
Layout-driven RF design creation——Analog / RF OptionAnalog / RF OptionAnalog / RF OptionAnalog / RF Option
Flexible Shape Editor——Analog / RF OptionAnalog / RF OptionAnalog / RF OptionAnalog / RF Option
SIGNAL INTEGRITY
Pre- & Post-route signal integrity analysisView technical demoPre Route✓✓✓✓✓
Graphical topology definition and explorationPre Route✓✓✓✓✓
Interactive waveform viewerPre Route✓✓✓✓✓
IBIS 5.0 supportPre Route✓✓✓✓✓
Lossy transmission linesPre Route✓✓✓✓✓
Coupled (3 net) simulation Pre-RoutePre Route✓✓✓✓✓
Differential pair exploration and simulationPre Route✓✓✓✓✓
PSpice SIMULATION
Simulation capacity: 250 Nodes, 250 devices, 1M Transient, 10K AC / DC Sweep, limits✓✓PSpice System DesignerPSpice System DesignerPSpice System DesignerPSpice System Designer
Analog Devices: all except BSIM 3.3, BSIM4, Magnetic Core, IGBT, Tlines, DMI✓✓PSpice System DesignerPSpice System DesignerPSpice System DesignerPSpice System Designer
Analog behavioural modelling✓✓PSpice System DesignerPSpice System DesignerPSpice System DesignerPSpice System Designer
Digital Devices: All✓✓PSpice System DesignerPSpice System DesignerPSpice System DesignerPSpice System Designer
Learning PSpice Free TemplatesView technical demo✓✓PSpice System DesignerPSpice System DesignerPSpice System DesignerPSpice System Designer
Bias Point, DC sweep, AC sweep and Transient analysis (with Temperature)View technical demo✓✓PSpice System DesignerPSpice System DesignerPSpice System DesignerPSpice System Designer
Bias point voltages, currents and power display in Schematic✓✓PSpice System DesignerPSpice System DesignerPSpice System DesignerPSpice System Designer
Modelling Application in Capture✓✓PSpice System DesignerPSpice System DesignerPSpice System DesignerPSpice System Designer
Parametric SweepView technical demo✓✓PSpice System DesignerPSpice System DesignerPSpice System DesignerPSpice System Designer
Monte Carlo / Worst CaseView technical demo✓✓PSpice System DesignerPSpice System DesignerPSpice System DesignerPSpice System Designer
Check Point restart✓✓PSpice System DesignerPSpice System DesignerPSpice System DesignerPSpice System Designer
Auto Convergence, Advanced Convergence and Speed Mode✓✓PSpice System DesignerPSpice System DesignerPSpice System DesignerPSpice System Designer
Interactive waveform viewer and analyzer✓✓PSpice System DesignerPSpice System DesignerPSpice System DesignerPSpice System Designer
Waveform: FFT✓✓PSpice System DesignerPSpice System DesignerPSpice System DesignerPSpice System Designer
Advanced tools: FRA, Core loss✓✓PSpice System DesignerPSpice System DesignerPSpice System DesignerPSpice System Designer
PSpice video: Example Design Simple Circuit 1View technical demo✓✓PSpice System DesignerPSpice System DesignerPSpice System DesignerPSpice System Designer
PSpice video: Example Design Simple Circuit 2View technical demo✓✓PSpice System DesignerPSpice System DesignerPSpice System DesignerPSpice System Designer
PSpice video: Example Design Simple Circuit 3View technical demo✓✓PSpice System DesignerPSpice System DesignerPSpice System DesignerPSpice System Designer
PSpPice video: Example Design Simple Circuit 4View technical demo✓✓PSpice System DesignerPSpice System DesignerPSpice System DesignerPSpice System Designer
PSpice video: Example Design Simple Circuit 5View technical demo✓✓PSpice System DesignerPSpice System DesignerPSpice System DesignerPSpice System Designer
PSpice video: Example Design Simple Circuit 6View technical demo✓✓PSpice System DesignerPSpice System DesignerPSpice System DesignerPSpice System Designer
PSpice video: Example Design Simple Circuit 7View technical demo✓✓PSpice System DesignerPSpice System DesignerPSpice System DesignerPSpice System Designer
Performance AnalysisPSpice DesignerPSpice DesignerPSpice System DesignerPSpice System DesignerPSpice System DesignerPSpice System Designer
Model Editor, Stimulus Editor, Magnetic Parts EditorPSpice DesignerPSpice DesignerPSpice System DesignerPSpice System DesignerPSpice System DesignerPSpice System Designer
Advanced Analysis: Smoke (Stress)PSpice DesignerPSpice DesignerPSpice System DesignerPSpice System DesignerPSpice System DesignerPSpice System Designer
Advanced Analysis: Optimiser, Sensitivity, Monte CarloPSpice Designer PlusPSpice Designer PlusPSpice System DesignerPSpice System DesignerPSpice System DesignerPSpice System Designer
Advanced Analysis: Parametric PlotterPSpice Designer PlusPSpice Designer PlusPSpice System DesignerPSpice System DesignerPSpice System DesignerPSpice System Designer
PSpice - MATLAB Interface: Co-Simulation, Visualisation, FunctionsPSpice Designer PlusPSpice Designer PlusPSpice System DesignerPSpice System DesignerPSpice System DesignerPSpice System Designer
Analog Devices: AllPSpice DesignerPSpice DesignerPSpice System DesignerPSpice System DesignerPSpice System DesignerPSpice System Designer
Simulation capacity: unlimitedPSpice DesignerPSpice DesignerPSpice System DesignerPSpice System DesignerPSpice System DesignerPSpice System Designer
Sigrity power integrity analysis on a PCBFree Sigrity E-book download PDF here →

Customer stories

Designed with Cadence Allegro X

VSORA

Designed with Cadence Allegro X

SpiNNaker

Designed with Cadence Allegro X

Raspberry Pi

Designed with Cadence Allegro X

Proof of standing

Engineering expertise, built since 1997.

A Cadence approved software, training and services partner for engineering and procurement teams across the UK and Ireland.

1997

Supporting electronic design teams since.

UK + IE

Local software, training and support.

EDA

From schematic capture to sign-off.