Lab 19-2: Misled Worst-Case 17.4

November 12, 2019 admin

All content Copyright 2022 Parallel Systems Ltd.

 

1. If necessary, open the circuit from the previous lab.

 

2. Leave the Probe Window open but return to the schematic.

 

3. Edit the PSpice model for Rbmod, change it to look like the following:

.model Rbmod RES (R=1.1 dev=5%)

 

4. Save the model and return to Capture.

 

5. Rerun the Worst Case analysis.

 

6. Examine the results in the output file. An excerpt is shown below.

WORST CASE SUMMARY

*******************************************************************

The range is ( 9.90000E+04 to 1.01000E+05)

RUN MINIMUM VALUE

WORST CASE ALL DEVICES

79.641 at F = 100.0000E+03

( 56.575% of Nominal)

JOB CONCLUDED

 

7. Go back to Capture and rerun the parametric analysis.

 

8. Use the cursor search command again to find the new worst case point listed in the output file, 79.641, and mark the point.

 

9. Examine the following picture.

What We Are Seeing

In the figure above, the reported worse-case and the actual worst-case have been marked. When we used the first model definition we used, the nominal value of Rbmod was left at 720 ohms. The sensitivity analysis increments R by a small amount and checks its effect on V(OUT). This slight increase in R causes an increase in the base bias voltage of the BJT, and increases the amplifier’s gain, V(OUT). The worst-case correctly sets R to its minimum value for the lowest possible V(OUT) for the resistor value range.

 

The second model statement scales the nominal value of Rb2 by 1.1 to approximately 880 ohms. The gain still increases with a small increase in R, but a larger increase in R increases the base voltage so much that it drives the BJT into saturation and nearly eliminates the gain. The worst-case analysis is fooled by the sensitivity analysis into assuming that Rb2 must be minimized to degrade the gain, but maximizing Rb2 is much worse.

 

Note that even an optimizer that checks the local gradient to determine how the parameters should be varied is fooled by this circuit.

 

 

End of Lab

 

 

All content Copyright 2022 Parallel Systems Ltd.