Mixing analog and digital components in a schematic will activate the I/O models when the simulation is run. These will appear as “D to A” and “A to D” models added to the netlist output to convert between the State of the digital simulation and Voltage levels of the analog simulation. This is done “transparently” as far as the simulation is concerned.

The “mixed” simulation results will appear in the Probe window on a single X, time, axis, with the waveforms split into a plot for the “state” of the digital nodes and another plot for the analog Voltage levels.

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