All content Copyright 2022 Parallel Systems Ltd.

 

1. Select File>Open>Project from the top menu.

 

2. Browse to the C:\OrCAD_Training\Capture\training directory and open the training.opj file.

 

3. In the Project Manager window, double-click on .\training.dsn to expand the contents of the design file. (If they are not already expanded)

Observe that the design contains three schematic folders (Release Root Schematic, Data Schematic, and HSRAM).

 

4. Observe the forward slash on the folder icon for the Release Root Schematic.

The forward slash indicates the schematic is the ‘root’ or top level of the hierarchy.

 

5. Left-click the plus (+) signs next to each of the schematic folders to display their contents.

Each of these folders contains a single schematic page, except the Release Root Schematic, which has two.

 

6. In the Release Root Schematic folder, double-click on Page2 to open it.

 

7. If necessary, enlarge the schematic window, and zoom to all.

 

8. In the schematic window, locate the hierarchical blocks named High Speed Ram and Data Schematic.

 

9. In the schematic window, double-click on the High Speed Ram block symbol to descend into, and open, the underlying schematic.

(A right-click> Descend Hierarchy with the block selected would also descend into, and open, the underlying schematic)

This is the circuitry that the hierarchical block represents.

 

10. Close the High Speed Ram schematic window.

The Release Root Schematic window should still be open.

 

11. In the schematic window, double-click on the Data Schematic block symbol to descend into, and open, the underlying schematic.

 

12. Close the Data Schematic window.

Note

In this lesson, you will work with the Release Root Schematic, pages 1 and 2, only.

 

 

End of Lab

 

All content Copyright 2022 Parallel Systems Ltd.